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3.2.39
c11, DMA External Start Address Register
U bit
DMA bit
0
0
1
1
0
1
ARM DDI 0301H
ID012310
The memory attributes for that VA are used in the transfer, so memory permission faults might
be generated. The Internal Start Address must lie within a TCM, otherwise an error is reported
in the DMA Channel Status Register. The marking of memory locations in the TCM as being
Device results in Unpredictable effects. The global system behavior, but not the security, can be
affected.
The contents of this register do not change while the DMA channel is Running. When the
channel is stopped because of a Stop command, or an error, it contains the address required to
restart the transaction. On completion, it contains the address equal to the Internal End Address.
The Internal Start Address must be aligned to the transaction size set in the DMA Control
Register or the processor generates a bad parameter error.
The purpose of the DMA External Start Address Register for each channel is to define the first
address in external memory for that DMA channel. That is, it defines the first address that data
transfers go to or from.
The DMA External Start Address Register is:
•
in CP15 c11
•
one 32-bit read/write register for each DMA channel common to Secure and Non-secure
worlds
•
accessible in user and privileged modes.
The DMA External Start Address Register bits [31:0] contain the External Start VA.
Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control
Register on page 3-55. The processor can access this register in User mode if the U bit, see c11,
DMA User Accessibility Register on page 3-107, for the currently selected channel is set to 1.
Table 3-115 lists the results of attempted access for each mode.
Table 3-115 Results of access to the DMA External Start Address Register
Secure Privileged
Read or Write
Data
Data
Data
Data
To access the DMA External Start Address Register set the DMA Channel Number Register to
the appropriate DMA channel and read or write CP15 with:
•
Opcode_1 set to 0
•
CRn set to c11
•
CRm set to c6
•
Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c11, c6, 0
MCR p15, 0, <Rd>, c11, c6, 0
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Non-secure Privileged
Read or Write
Undefined exception
Data
Undefined exception
Data
; Read DMA External Start Address Register
; Write DMA External Start Address Register
System Control Coprocessor
Secure User
Non-secure User
Read or Write
Read or Write
Undefined exception
Undefined exception
Undefined exception
Undefined exception
Data
Undefined exception
Data
Data
3-115
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