ARM ARM1176JZF-S Technical Reference Manual page 53

ARM DDI 0301H
ID012310
The Fetch stages can hold up to four instructions, where branch prediction is performed on
instructions ahead of execution of earlier instructions.
The Issue and Decode stages can contain any instruction in parallel with a predicted branch.
The Execute, Memory, and Write stages can contain a predicted branch, an ALU or multiply
instruction, a load/store multiple instruction, and a coprocessor instruction in parallel execution.
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