Table 2-1 Write Access Behavior For System Control Processor Registers - ARM ARM1176JZF-S Technical Reference Manual

2.2.3 TrustZone write access disable
Register
Secure Control Register
Secure Translation Table Base
Register 0
Secure Translation Table Control
Register
Secure Domain Access Control
Register
Data TCM Non-secure Control
Access Register
ARM DDI 0301H
ID012310
Secure peripherals require Secure device drivers to supervise them. To minimize the effects of
drivers on system security it is recommended that the Secure device drivers run in the Secure
User mode so that they cannot change the NS bit directly.
Secure debug
For details of software debug in Secure systems see, Chapter 13 Debug. Because the processor
boots in Secure mode you might have to make special arrangements to debug code not written
for TrustZone.
The processor pin CP15SDISABLE disables write access to certain registers in the system
control coprocessor. Table 2-1 lists the registers affected by this pin.
Attempts to write to the registers in Table 2-1 when CP15SDISABLE is HIGH result in an
Undefined exception. Reads from the registers are still permitted. For more information about
the registers, see Chapter 3 System Control Coprocessor.
A change to the CP15SDISABLE pin takes effect on the instructions decoded by the processor
as quickly as practically possible. Software must perform a Prefetch Flush CP15 operation, after
a change to this pin on the boundary of the macrocell, to ensure that its effect is recognized for
following instructions. It it is expected that:
control of the CP15SDISABLE pin remains within the SoC that embodies the macrocell
•
the CP15SDISABLE pin is set to logic 0 by the SoC hardware at reset.
•
You can use the CP15SDISABLE pin to disable subsequent access to system control processor
registers after the Secure boot code runs and protect the configuration that the Secure boot code
applies.
Note
With the exception of the TCM Region Registers, the registers in Table 2-1 are only accessible
in Secure Privileged modes.

Table 2-1 Write access behavior for system control processor registers

Instruction that is Undefined
when CP15SDISABLE=1
MCR p15, 0, Rd, c1, c0, 0
MCR p15, 0, Rd, c2, c0, 0
MCR p15, 0, Rd, c2, c0, 2
MCR p15, 0, Rd, c3, c0, 0
MCR p15, 0, Rd, c9, c1, 2
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Programmer's Model
Security Condition
Secure Monitor or Privileged when NS=0
Secure Monitor or Privileged when NS=0
Secure Monitor or Privileged when NS=0
Secure Monitor or Privileged when NS=0
Secure Monitor or Privileged when NS=0
2-9