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3.2.23
c8, TLB Operations Register
ARM DDI 0301H
ID012310
The purpose of the TLB Operations Register is to either:
•
invalidate all the unlocked entries in the TLB
•
invalidate all TLB entries for an area of memory before the MMU remaps it
•
invalidate all TLB entries that match an ASID value.
These operations can be performed on either:
•
Instruction TLB
•
Data TLB
•
Unified TLB.
Note
The ARM1176JZF-S processor has a unified TLB. Any TLB operations specified for the
Instruction or Data TLB perform the equivalent operation on the unified TLB.
The TLB Operations Register is:
•
in CP15 c8
•
a 32-bit write-only register banked for Secure and Non-secure world operations
•
accessible in privileged modes only.
Table 3-82 lists the results of attempted access for each mode.
Secure Privileged
Read
Write
Undefined exception
Secure data
To access the TLB Operations Register write CP15 with:
•
Opcode_1 set to 0
•
CRn set to c8
•
CRm set to:
—
c5, Instruction TLB
—
c6, Data TLB
—
c7, Unified TLB
•
Opcode_2 set to:
—
0, Invalidate TLB unlocked entries
—
1, Invalidate TLB Entry by MVA
—
2, Invalidate TLB Entry on ASID Match.
For example, to invalidate all the unlocked entries in the Instruction TLB:
MCR p15,0,<Rd>,c8, c5,0
Functions that update the contents of the TLB occur in program order. Therefore, an explicit
data access before the TLB function uses the old TLB contents, and an explicit data access after
the TLB function uses the new TLB contents. For instruction accesses, TLB updates are
guaranteed to have taken effect before the next pipeline flush. This includes Flush Prefetch
Buffer operations and exception return sequences.
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Table 3-82 Results of access to the TLB Operations Register
Non-secure Privileged
Read
Undefined exception
; Write TLB Operations Register
System Control Coprocessor
User
Write
Non-secure data
Undefined exception
3-86
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