Figure 2-6 Register Organization In Arm State - ARM ARM1176JZF-S Technical Reference Manual

System and
User
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
CPSR
= banked register
ARM DDI 0301H
ID012310
ARM state general registers and program counter
FIQ Supervisor
R0 R0
R1 R1
R2 R2
R3 R3
R4 R4
R5 R5
R6 R6
R7 R7
R8_fiq R8
R9_fiq R9
R10_fiq R10
R11_fiq R11
R12_fiq R12
R13_fiq R13_svc
R14_fiq R14_svc
R15 (PC) R15 (PC)
ARM state program status registers
CPSR CPSR
SPSR_fiq SPSR_svc
Figure 2-7 on page 2-21 shows an alternative view of the ARM registers.
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Abort IRQ
R0 R0
R1 R1
R2 R2
R3 R3
R4 R4
R5 R5
R6 R6
R7 R7
R8 R8
R9 R9
R10 R10
R11 R11
R12 R12
R13_abt R13_irq
R14_abt R14_irq
R15 (PC) R15 (PC)
CPSR CPSR
SPSR_abt SPSR_irq

Figure 2-6 Register organization in ARM state

Programmer's Model
Secure
Undefined
monitor
R0 R0
R1 R1
R2 R2
R3 R3
R4 R4
R5 R5
R6 R6
R7 R7
R8 R8
R9 R9
R10 R10
R11 R11
R12 R12
R13_und R13_mon
R14_und R14_mon
R15 (PC) R15 (PC)
CPSR CPSR
SPSR_und SPSR_mon
2-20