ARM ARM1176JZF-S Technical Reference Manual page 753

Load/store architecture
Load Store Unit (LSU)
LSU
Macrocell
Memory bank
Memory coherency
Memory Management Unit (MMU)
Microprocessor
Miss
MMU
Modified Virtual Address (MVA)
Monitor debug-mode
Multi-ICE
Multi-layered
Multi master
MVA
ARM DDI 0301H
ID012310
- a byte at a halfword-aligned address is the least significant byte within the halfword at that
address.
See also Big-endian memory.
A processor architecture where data-processing operations only operate on register contents, not
directly on memory contents.
The part of a processor that handles load and store transfers.
See Load Store Unit.
A complex logic block with a defined interface and behavior. A typical VLSI system comprises
several macrocells, such as a processor, an ETM, and a memory block, plus application-specific
logic.
One of two or more parallel divisions of interleaved memory, usually one word wide, that enable
reads and writes of multiple words at a time, rather than single words. All memory banks are
addressed simultaneously and a bank enable or chip select signal determines which of the banks
is accessed for each transfer. Accesses to sequential word addresses cause accesses to sequential
banks. This enables the delays associated with accessing a bank to occur during the access to its
adjacent bank, speeding up memory transfers.
A memory is coherent if the value read by a data read or instruction fetch is the value that was
most recently written to that location. Memory coherency is made difficult when there are
multiple possible physical locations that are involved, such as a system that has main memory,
a write buffer and a cache.
Hardware that controls caches and access permissions to blocks of memory, and translates
virtual addresses to physical addresses.
See Processor.
See Cache miss.
See Memory Management Unit.
A Virtual Address produced by the ARM processor can be changed by the current Process ID
to provide a Modified Virtual Address (MVA) for the MMUs and caches.
See also Fast Context Switch Extension.
One of two mutually exclusive debug modes. In Monitor debug-mode the processor enables a
software abort handler provided by the debug monitor or operating system debug task. When a
breakpoint or watchpoint is encountered, this enables vital system interrupts to continue to be
serviced while normal program execution is suspended.
See also Halting debug-mode.
A JTAG-based tool for debugging embedded systems.
An AMBA scheme to break a bus into segments that are controlled in access. This enables local
masters to reduce lock overhead.
An AMBA bus sharing scheme (not in AMBA Lite) where different masters can gain a bus lock
(Grant) to access the bus in an interleaved fashion.
See Modified Virtual Address.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Glossary
Glossary-14