ARM ARM1176JZF-S Technical Reference Manual page 673

ARM DDI 0301H
ID012310
Table 21-5 Double-precision source register clearing for two-cycle instructions
Execute 1 cycle
4
5
6
7
8
For the following two-cycle, double-precision, short vector instruction, the LEN field contains
b011, selecting a vector length of four iterations:
FMULD D4, D8, D12
The FMULD instruction performs the following operations:
FMULD D4, D8, D12
FMULD D5, D9, D13
FMULD D6, D10, D14
FMULD D7, D11, D15
In full-compliance mode, the source scoreboard clears the source registers of each iteration in
the first Execute 1 cycle of the iteration.
In RunFast mode, only the third iteration source registers, D10 and D14, and the fourth iteration
source registers, D11 and D15, are locked. The source scoreboard clears D10 and D14 in the
first Execute 1 cycle and clears D11 and D15 in the third Execute 1 cycle of the instruction.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Source registers cleared in Execute 1 stage of each iteration
Full-compliance mode
-
Iteration 3 registers
-
Iteration 4 registers
-
VFP Instruction Execution
RunFast mode
-
-
-
-
-
21-12