Table 3-117 Dma Channel Status Register Bit Functions; Figure 3-63 Dma Channel Status Register Format - ARM ARM1176JZF-S Technical Reference Manual

3.2.41 c11, DMA Channel Status Register
Bits Field name
[31:17] -
[16] ESX[0]
[15:14] -
[13] ISX[0]
ARM DDI 0301H
ID012310
The Internal End Address is the final internal address, modulo the transaction size, that the
DMA is to access plus the transaction size. Therefore, the Internal End Address is the first,
incremented, address that the DMA does not access.
If the Internal End Address is the same of the Internal Start Address, the DMA transfer
completes immediately without performing transactions.
When the transaction associated with the final internal address has completed, the whole DMA
transfer is complete.
The Internal End Address is a VA. Page tables describe the physical mapping of the VA when
the channel starts.
The memory attributes for that VA are used in the transfer, so memory permission faults might
be generated. The Internal End Address must lie within a TCM, otherwise an error is reported
in the DMA Channel Status Register. The marking of memory locations in the TCM as being
Device results in Unpredictable effects. The global system behavior, but not the security, can be
affected.
The Internal End Address must be aligned to the transaction size set in the DMA Control
Register or the processor generates a bad parameter error.
The purpose of the DMA Channel Status Register for each channel is to define the status of the
most recently started DMA operation on that channel.
The DMA Channel Status Register is:
• in CP15 c11
• one 32-bit read-only register for each DMA channel common to Secure and Non-secure
worlds
• accessible in user and privileged modes.
Figure 3-63 shows the bit arrangement for the DMA Channel Status Register.
31
SBZ/UNP
Table 3-117 lists the functions of the bits in the DMA Channel Status Register.
Function
UNP/SBZ.
The ESX[0] bit adds a SLVERR or DECERR qualifier to the ES encoding. Only predictable
on ES encodings of b11010, b11100, and b1.1110, otherwise UNP/SBZ. For the predictable
encodings:0 = DECERR1 = SLVERR.
UNP/SBZ.
The ISX[0] bit adds a SLVERR or DECERR qualifier to the IS encoding. Only predictable on
IS encodings of b11100 and b11110, otherwise UNP/SBZ. For the predictable encodings:0 =
DECERR1 = SLVERR.
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17 16 15 14 13 12 11
SBZ/ B
UNP P
ESX[0] ISX[0]

Figure 3-63 DMA Channel Status Register format

Table 3-117 DMA Channel Status Register bit functions

System Control Coprocessor
7 6 2 1 0
ES IS
Status
3-117