ARM ARM1176JZF-S Technical Reference Manual page 66

Operation
Saturate, select,
and pack
ARM DDI 0301H
ID012310
Signed (high 16 x 16) +
(low 16 x 16), and set Q flag
As SMUAD , but high x low,
low x high, and set Q flag
Signed (high 16 x 16) -
(low 16 x 16)
As SMUSD , but high x low,
low x high
Truncated high 16 (32 x 32)
Rounded high 16 (32 x 32)
Unsigned 32 x 32, + two 32, to 64
Signed saturation at
bit position n
Unsigned saturation at
bit position n
Two 16 signed saturation at
bit position n
Two 16 unsigned saturation at
bit position n
Select bytes from Rn / Rm
on GE flags
Pack low 16/32, high 16/32
Pack high 16/32, low 16/32
Table 1-8 summarizes addressing mode 2.
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Table 1-7 ARM instruction set summary (continued)
Assembler
SMUAD{cond} <Rd>, <Rm>, <Rs>
SMUADX{cond} <Rd>, <Rm>, <Rs>
SMUSD{cond} <Rd>, <Rm>, <Rs>
SMUSDX{cond} <Rd>, <Rm>, <Rs>
SMMUL{cond} <Rd>, <Rm>, <Rs>
SMMULR{cond} <Rd>, <Rm>, <Rs>
UMAAL{cond} <RdLo>, <RdHi>, <Rm>, <Rs>
SSAT{cond} <Rd>, #<immed_5>, <Rm>{, <shift>}
USAT{cond} <Rd>, #<immed_5>, <Rm>{, <shift>}
SSAT16{cond} <Rd>, #<immed_4>, <Rm>
USAT16{cond} <Rd>, #<immed_4>, <Rm>
based SEL{cond} <Rd>, <Rn>, <Rm>
PKHBT{cond} <Rd>, <Rn>, <Rm>{, LSL #<immed_5>}
PKHTB{cond} <Rd>, <Rn>, <Rm>{, ASR #<immed_5>}
Addressing mode
Offset
Immediate offset
Zero offset
Register offset
Scaled register offset
Introduction
Table 1-8 Addressing mode 2
Assembler
-
[<Rn>, #+/<immed_12>]
[<Rn>]
[<Rn>, +/-<Rm>]
[<Rn>, +/-<Rm>, LSL #<immed_5>]
[<Rn>, +/-<Rm>, LSR #<immed_5>]
[<Rn>, +/-<Rm>, ASR #<immed_5>]
[<Rn>, +/-<Rm>, ROR #<immed_5>]
[<Rn>, +/-<Rm>, RRX]
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