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Cacheable Write-Through or Noncacheable STM11 ................................................................ 8-33
Cacheable Write-Through or Noncacheable STM12 ................................................................ 8-34
Cacheable Write-Through or Noncacheable STM13 ................................................................ 8-34
Cacheable Write-Through or Noncacheable STM14 ................................................................ 8-35
Cacheable Write-Through or Noncacheable STM15 ................................................................ 8-35
Cacheable Write-Through or Noncacheable STM16 ................................................................ 8-36
Example Peripheral Interface reads and writes ........................................................................ 8-37
Reset modes ............................................................................................................................. 9-10
Coprocessor instructions .......................................................................................................... 11-3
Coprocessor control signals ...................................................................................................... 11-4
Pipeline stage update ............................................................................................................... 11-7
Addressing of queue buffers ................................................................................................... 11-10
Retirement conditions ............................................................................................................. 11-20
VIC port signals ......................................................................................................................... 12-3
Terms used in register descriptions .......................................................................................... 13-5
CP14 debug register map ......................................................................................................... 13-5
Debug ID Register bit field definition ......................................................................................... 13-7
Debug Status and Control Register bit field definitions ............................................................. 13-8
Data Transfer Register bit field definitions .............................................................................. 13-12
Vector Catch Register bit field definitions ............................................................................... 13-14
Summary of debug entry and exception conditions ................................................................ 13-14
Processor breakpoint and watchpoint registers ...................................................................... 13-16
Breakpoint Value Registers, bit field definition ........................................................................ 13-17
Processor Breakpoint Control Registers ................................................................................. 13-17
Breakpoint Control Registers, bit field definitions ................................................................... 13-18
Meaning of BCR[22:20] bits .................................................................................................... 13-19
Processor Watchpoint Value Registers .................................................................................. 13-20
Watchpoint Value Registers, bit field definitions ..................................................................... 13-21
Processor Watchpoint Control Registers ................................................................................ 13-21
Watchpoint Control Registers, bit field definitions ................................................................... 13-21
Debug State Cache Control Register bit functions ................................................................. 13-23
Debug State MMU Control Register bit functions ................................................................... 13-24
CP14 debug instructions ......................................................................................................... 13-26
Debug instruction execution .................................................................................................... 13-27
Secure debug behavior ........................................................................................................... 13-28
Behavior of the processor on debug events ........................................................................... 13-33
Setting of CP15 registers on debug events ............................................................................ 13-34
Values in the link register after exceptions ............................................................................. 13-36
Read PC value after Debug state entry .................................................................................. 13-39
Example memory operation sequence ................................................................................... 13-41
Supported public instructions .................................................................................................... 14-6
Scan chain 7 register map ...................................................................................................... 14-19
Instruction interface signals ...................................................................................................... 15-2
ETMIACTL[17:0] ....................................................................................................................... 15-3
ETMIASECCTL[1:0] .................................................................................................................. 15-4
Data address interface signals .................................................................................................. 15-4
ETMDACTL[17:0] ...................................................................................................................... 15-5
Data value interface signals ...................................................................................................... 15-6
ETMDDCTL[3:0] ....................................................................................................................... 15-6
ETMPADV[2:0] .......................................................................................................................... 15-6
Coprocessor interface signals ................................................................................................... 15-7
ETMCPSECCTL[1:0] format ..................................................................................................... 15-7
Other connections ..................................................................................................................... 15-8
Pipeline stages .......................................................................................................................... 16-3
Definition of cycle timing terms ................................................................................................. 16-5
Register interlock examples ...................................................................................................... 16-6
Data Processing Instruction cycle timing behavior if destination is not PC ............................... 16-7
Data Processing Instruction cycle timing behavior if destination is the PC ............................... 16-7
QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior ................................... 16-9
ARMv6 media data-processing instructions cycle timing behavior ......................................... 16-10
ARM DDI 0301H
ID012310
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