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14.8.5
Leaving Debug state
ARM DDI 0301H
ID012310
RTI
INST 0x0 Ready
Until Ready == 1
SCAN_N 1
DATAOUT readDSCR
Until readDSCR[7]==1
SCAN_N 4
INST NOP
RTI
LOOP
INST 0 Ready
Until Ready == 1
SCAN_N 1
DATAOUT readDSCR
6.
Store out R0. It is going to be used to save the rDTR. Use the standard sequence of
Reading a current mode ARM register in the range R0-R14 on page 14-34. Scan chain 5
and INTEST are now selected.
7.
Save the rDTR and the rDTRempty bit in three steps:
a.
The rDTRempty bit is the inverted version of DSCR[30], saved in step 2. If
DSCR[30] is clear, register empty, there is no requirement to read the rDTR, go to 7.
b.
Transfer the contents of rDTR to R0:
ITRSEL
INST
MRC p14,0,R0,c0,c5,0
RTI
LOOP
INST 0x00000000 Ready
UNTIL Ready==1
c.
Read R0 using the standard sequence of Reading a current mode ARM register in
the range R0-R14 on page 14-34.
8.
Store out CPSR using the standard sequence of Reading the CPSR/SPSR on page 14-35.
9.
Store out PC using the standard sequence of Reading the PC on page 14-36.
10.
Adjust the PC to enable you to resume execution later:
•
subtract
from the stored value if the processor was in ARM state when entering
0x8
Debug state
•
subtract
0x4
from the stored value if the processor was in Thumb state when entering
Debug state
•
subtract
from the stored value if the processor was in Jazelle state when entering
0x0
Debug state.
These values are not dependent on the Debug state entry method. See Behavior of the PC
in Debug state on page 13-38. The entry state can be determined by examining the T and
J bits of the CPSR.
11.
Cache and MMU preservation measures must also be taken here. This includes saving all
the relevant CP15 registers using the standard coprocessor register reading sequence that
Coprocessor register reads and writes on page 14-38 describes.
To leave Debug state:
1.
Restore standard ARM registers for all modes, except R0, PC, and CPSR.
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; NOP takes the
; imprecise Data Aborts
; clears DSCR[7]
; select the ITR and EXTEST
; instruction to copy CP14's debug
; register c5 into R0
; wait until the instruction ends
Debug Test Access Port
14-32
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