Table 3-111 Results Of Access To The Dma Enable Registers - ARM ARM1176JZF-S Technical Reference Manual

U DMA
bit bit
0 0
1
1 0
1
ARM DDI 0301H
ID012310
• the interrupt that is set by the DMA channel as a result of an error or
completion, see c11, DMA Control Register on page 3-112 for more details.
The Clear command does not change the contents of the Internal and External
Start Address Registers. A Clear command has no effect when the channel status
is Running or Queued.
Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control
Register on page 3-55. The processor can access these registers in User mode if the U bit, see
c11, DMA User Accessibility Register on page 3-107, for the currently selected channel is set to
1. Table 3-111 lists the results of attempted access for each mode.
Secure Non-secure
Privileged Privileged
Read Write Read
Undefined Data Undefined
exception exception
Undefined Data Undefined
exception exception
Undefined Data Undefined
exception exception
Undefined Data Undefined
exception exception
To access a DMA Enable Register set the DMA Channel Number Register to the appropriate
DMA channel and write CP15 with:
• Opcode_1 set to 3
• CRn set to c11
• CRm set to c3
• Opcode_2 set to:
— 0, Stop
— 1, Start
— 2, Clear.
For example:
MCR p15, 0, <Rd>, c11, c3, 0
MCR p15, 0, <Rd>, c11, c3, 1
MCR p15, 0, <Rd>, c11, c3, 2
Debug implications for the DMA
The level one DMA behaves as a separate engine from the processor core, and when started,
works autonomously. When the level one DMA has channels with the status of Running or
Queued, these channels continue to run, or start running, even if a debug mechanism stops the
processor. This can cause the contents of the TCM to change while the processor stops in debug.
To avoid this situation you must ensure the level one DMA issues a Stop command to stop
Running or Queued channels when entering debug.
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Table 3-111 Results of access to the DMA enable registers

Secure User
Write Read Write
Undefined Undefined Undefined
exception exception exception
Data Undefined Undefined
exception exception
Undefined Undefined Data
exception exception
Data Undefined Data
exception
; Stop DMA Enable Register
; Start DMA Enable Register
; Clear DMA Enable Register
System Control Coprocessor
Non-secure User
Read Write
Undefined Undefined
exception exception
Undefined Undefined
exception exception
Undefined Undefined
exception exception
Undefined Data
exception
3-111