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8.3.1
Channel definition
ARM DDI 0301H
ID012310
Each of the five independent channels consists of a set of information signals and uses a
two-way VALID and READY handshake mechanism.
The information source uses the VALID signal to show when valid data is available on the
channel. The destination uses the READY signal to show when it can accept the data. Both the
read data channel and the write data channel also include a LAST signal to indicate when the
transfer of the final data item within a transaction takes place.
Read Address channel
The read address channel is used in every transaction and carries all the required read address
and control information for that transaction. The AXI supports the following mechanisms:
•
variable-length bursts, from 1 to 16 data transfers per burst
•
bursts with a transfer size of eight bits up to the maximum data bus width
•
wrapping, incrementing, and fixed address bursts
•
atomic operations, using exclusive and locked access
•
system-level caching and buffering control
•
Secure and privileged access.
Write address channel
The write address channel is used in every transaction and carries all the required write address
and control information for that transaction. The AXI supports the following mechanisms:
•
variable-length bursts, from 1 to 16 data transfers per burst
•
bursts with a transfer size of eight bits up to the maximum data bus width
•
wrapping, incrementing, and fixed address bursts
•
atomic operations, using exclusive and locked access
•
system-level caching and buffering control
•
Secure and privileged access.
Read data channel
The read data channel conveys both the read data and any read response information from the
slave back to the master. The read data channel includes:
•
the data bus, that is 32 bits wide for the Peripheral port, and 64 bits wide for the Data
Read/Write port, Instruction port and DMA port
•
a read response indicating the completion status of the read transaction.
Write data channel
The write data channel conveys the write data from the master to the slave and includes:
•
the data bus, that is 32 bits wide for the Peripheral port, and 64 bits wide for the Data
Read/Write port, Instruction port and DMA port
•
one byte lane strobe for every eight data bits, indicating the bytes of the data bus that are
valid.
Write response channel
The write response channel provides a way for the slave to respond to write transactions. All
write transactions use completion signaling.
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Level Two Interface
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