ARM ARM1176JZF-S Technical Reference Manual page 65

Operation
Sign/zero extend
and add
Signed multiply
and multiply,
accumulate
ARM DDI 0301H
ID012310
Two low 8/16, sign extend to 16 +
16
Low 8/32, sign extend to 32, + 32
Low 16/32, sign extend to 32, + 32
Two low 8/16, zero extend
to 16, + 16
Low 8/32, zero extend to 32, + 32
Low 16/32, zero extend to 32, + 32
Two low 8, sign extend to 16,
packed 32
Low 8, sign extend to 32
Low 16, sign extend to 32
Two low 8, zero extend to 16,
packed 32
Low 8, zero extend to 32
Low 16, zero extend to 32
Signed
(high 16 x 16) + (low 16 x 16) + 32,
and set Q flag.
As , but high x low,
SMLAD
low x high, and set Q flag
Signed
(high 16 x 16) - (low 16 x 16) + 32
As SMLSD , but high x low,
low x high
Signed
(high 16 x 16) + (low 16 x 16) + 64
As SMLALD , but high x low,
low x high
Signed
(high 16 x 16) - (low 16 x 16) + 64
As SMLSLD , but high x low,
low x high
32 + truncated high 16 (32 x 32)
32 + rounded high 16 (32 x 32)
32 - truncated high 16 (32 x 32)
32 -rounded high 16 (32 x 32)
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Table 1-7 ARM instruction set summary (continued)
Assembler
SXTAB16{cond} <Rd>, <Rn>, <Rm>{, <rotation>}
SXTAB{cond} <Rd>, <Rn>, <Rm>{, <rotation>}
SXTAH{cond} <Rd>, <Rn>, <Rm>{, <rotation>}
UXTAB16{cond} <Rd>, <Rn>, <Rm>{, <rotation>}
UXTAB{cond} <Rd>, <Rn>, <Rm>{, <rotation>}
UXTAH{cond} <Rd>, <Rn>, <Rm>{, <rotation>}
SXTB16{cond} <Rd>, <Rm>{, <rotation>}
SXTB{cond} <Rd>, <Rm>{, <rotation>}
SXTH{cond} <Rd>, <Rm>{, <rotation>}
UXTB16{cond} <Rd>, <Rm>,{, <rotation>}
UXTB{cond} <Rd>, <Rm>{, <rotation>}
UXTH{cond} <Rd>, <Rm>{, <rotation>}
SMLAD{cond} <Rd>, <Rm>, <Rs>, <Rn>
SMLADX{cond} <Rd>, <Rm>, <Rs>, <Rn>
SMLSD{cond} <Rd>, <Rm>, <Rs>, <Rn>
SMLSDX{cond} <Rd>, <Rm>, <Rs>, <Rn>
SMLALD{cond} <RdLo>, <RdHi>, <Rm>, <Rs>
SMLALDX{cond} <RdLo>, <RdHi>, <Rm>, <Rs>
SMLSLD{cond} <RdLo>, <RdHi>, <Rm>, <Rs>
SMLSLDX{cond} <RdLo>, <RdHi>, <Rm>, <Rs>
SMMLA{cond} <Rd>, <Rm>, <Rs>, <Rn>
SMMLAR{cond} <Rd>, <Rm>, <Rs>, <Rn>
SMMLS{cond} <Rd>, <Rm>, <Rs>, <Rn>
SMMLSR{cond} <Rd>, <Rm>, <Rs>, <Rn>
Introduction
1-39