Table 3-46 Secure Configuration Register Bit Functions; Figure 3-29 Secure Configuration Register Format - ARM ARM1176JZF-S Technical Reference Manual

3.2.10 c1, Secure Configuration Register
Bits
[31:7]
[6]
[5]
[4]
ARM DDI 0301H
ID012310
• CRn set to c1
• CRm set to c0
• Opcode_2 set to 2.
For example:
MRC p15, 0, <Rd>, c1, c0, 2
MCR p15, 0, <Rd>, c1, c0, 2
You must perform an Instruction Memory Barrier (IMB) sequence immediately after an update
of the Coprocessor Access Control Register, see Memory Barriers on page 5-8. You must not
attempt to execute any instructions that are affected by the change of access rights between the
IMB sequence and the register update.
To determine if any particular coprocessor exists in the system write the access bits for the
coprocessor of interest with a value other than b00. If the coprocessor does not exist in the
system the access rights remain set to b00.
The purpose of the Secure Configuration Register is to define:
• the current world as Secure or Non-secure
• the world in which the core executes exceptions
• the ability to modify the A and I bits in the CPSR in the Non-secure world.
The Secure Configuration Register is:
• in CP15 c1
• a 32 bit read/write register
• accessible in Secure privileged modes only.
Figure 3-29 shows the arrangement of bits in the register.
31
Table 3-46 lists how the bit values correspond with the Secure Configuration Register functions.
Field name Function
- UNP/SBZ.
nET The Early Termination bit is not implemented in ARM1176JZF-S processors.
UNP/SBZ.
AW Determines if the A bit in the CPSR can be modified when in the Non-secure world:
0 = Disable modification of the A bit in the CPSR in the Non-secure world, reset value
1 = Enable modification of the A bit in the CPSR in the Non-secure world.
FW Determines if the F bit in the CPSR can be modified when in the Non-secure world:
0 = Disable modification of the F bit in the CPSR in the Non-secure world, reset value
1 = Enable modification of the F bit in the CPSR in the Non-secure world.
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; Read Coprocessor Access Control Register
; Write Coprocessor Access Control Register
SBZ

Figure 3-29 Secure Configuration Register format

Table 3-46 Secure Configuration Register bit functions

System Control Coprocessor
7 6 5 4 3 2 1 0
n F
A F E IR N
E I
W W A Q S
T Q
3-52