16.11 Load And Store Double Instructions; Table 16-16 Load And Store Double Instructions Cycle Timing Behavior; Table 16-17 <Addr_Md_1Cycle> And <Addr_Md_2Cycle> Ldrd Example Instruction Explanation - ARM ARM1176JZF-S Technical Reference Manual

16.11 Load and Store Double instructions

Example instruction
Address is double-word aligned
LDRD R1, <addr_md_1cycle>
LDRD R1, <addr_md_2cycle>
Address not double-word aligned
LDRD R1, <addr_md_1cycle>
LDRD R1, <addr_md_2cycle>
a. Table 16-17 for an explanation of
Table 16-17 <addr_md_1cycle> and <addr_md_2cycle> LDRD example instruction explanation
Example instruction
<addr_md_1cycle>
ARM DDI 0301H
ID012310
This section describes the cycle timing behavior for the LDRD and STRD instructions
The LDRD and STRD instructions:
• Are two-cycle issue if either a negative register offset or a shift other than LSL #2 is used.
Only the offset register is an Early Reg.
• Are single-cycle issue if either a constant offset is used or if a register offset with no shift,
or shift by 2 is used. Both the base and any offset register are Early Regs.
• Take only one memory cycle if the address is doubleword aligned.
• Take two memory cycles if the address is not doubleword aligned.
The updated base register has a result latency of one. For back-to-back load/store instructions
with base write back, the updated base is available to the following load/store instruction with a
result latency of 0.
To prevent instructions after a STRD from writing to a register before it has stored that register,
the STRD registers have a lock latency that determines how many cycles it is before a
subsequent instruction that writes to that register can start.
Table 16-16 lists the cycle timing behavior for LDRD and STRD instructions.

Table 16-16 Load and Store Double instructions cycle timing behavior

Cycle
s
1
a
a 2
a 1
a 2
<addr_md_1cycle>
Table 16-17 lists the explanation of
uses.
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Result latency
Memory cycles
(LDRD)
1 3/3
2 4/4
2 3/4
3 4/5
and <addr_md_2cycle> .
<addr_md_1cycle>
Early Reg Comment
Cycle Timings and Interlock Behavior
Register lock latency
(STRD)
1,2
2,3
1,2
2,3
and <addr_md_2cycle> that Table 16-16
16-19