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21.7
Data hazards in full-compliance mode
21.7.1
Status register RAW hazard example
21.7.2
Load multiple-CDP RAW hazard example
ARM DDI 0301H
ID012310
The sections that follow give examples of data hazards in full-compliance mode:
•
Status register RAW hazard example
•
Load multiple-CDP RAW hazard example
•
CDP-CDP RAW hazard example on page 21-14
•
Load multiple-short vector CDP RAW hazard example on page 21-14
•
Short vector CDP-load multiple WAR hazard example on page 21-15.
In Example 21-4, the FMSTAT is stalled for four cycles in the Decode stage until the FCMPS
updates the condition codes in the FPSCR register. Two cycles later, the FMSTAT writes the
condition codes to the ARM11 processor.
FCMPS S1, S2
FMSTAT
Table 21-6 lists the VFP11 pipeline stages for Example 21-4.
Instruction
FCMPS
FMSTAT
In Example 21-5, the FADDS is stalled in the Issue stage for six cycles until the FLDM makes
its last transfer to the VFP11 coprocessor. S15 is forwarded from the load in cycle 9 to the
FADDS.
FLDM [Rx], {S8-S15}
FADDS S1, S2, S15
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Example 21-4 FCMPS-FMSTAT RAW hazard
Table 21-6 FCMPS-FMSTAT RAW hazard
Instruction cycle number
1
2
3
4
5
D
I
E1
E2
E3
-
D
D
D
D
Example 21-5 FLDM-FADDS RAW hazard
VFP Instruction Execution
6
7
8
9
10
E4
-
-
-
-
D
I
E
M1
M2
11
-
W
21-13
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