ARM ARM1176JZF-S Technical Reference Manual page 129

ARM DDI 0301H
ID012310
PC = 0xFFFF0010
else
PC = Secure_Base_Address + 0x00000010
Interrupt request (IRQ) exception
On an Interrupt Request, and CPSR[7]=0, I bit:
/* secure state is unchanged */
if SCR[1]=1 /* IRQ trapped in Secure Monitor mode */
R14_mon = address of the next instruction to be executed + 4
SPSR_mon = CPSR
CPSR [4:0] = 0b10110 /* Enter Secure Monitor mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [6] = 1 /* Disable fast interrupts */
CPSR [7] = 1 /* Disable interrupts */
CPSR [8] = 1 /* Disable imprecise aborts */
CPSR [9] = Secure EE-bit /* store value of secure Control Reg[25] */
CPSR[24] = 0 /* Clear J bit */
PC = Monitor_Base_Address + 0x00000018
else
R14_irq = address of the next instruction to be executed + 4
SPSR_irq = CPSR
CPSR [4:0] = 0b10010 /* Enter IRQ mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [7] = 1 /* Disable interrupts */
CPSR [8] = 1 /* Disable imprecise aborts */
CPSR [9] = Secure EE-bit /* store value of secure Control Reg[25] */
CPSR[24] = 0 /* Clear J bit */
if VE == 0 /* Core with VIC port only */
if high vectors configured then
PC = 0xFFFF0018
else
PC = Secure_Base_Address + 0x00000018
else
PC = IRQADDR
Fast Interrupt Request (FIQ) exception
On a Fast Interrupt Request, and CPSR[6]=0, F bit:
/* secure state is unchanged */
if SCR[2]=1 /* FIQ trapped in Secure Monitor mode */
R14_mon = address of the next instruction to be executed + 4
SPSR_mon = CPSR
CPSR [4:0] = 0b10110 /* Enter Secure Monitor mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [6] = 1 /* Disable fast interrupts */
CPSR [7] = 1 /* Disable interrupts */
CPSR [8] = 1 /* Disable imprecise aborts */
CPSR [9] = Secure EE-bit /* store value of secure Control Reg[25] */
CPSR[24] = 0 /* Clear J bit */
PC = Monitor_Base_Address + 0x0000001C
else
R14_fiq = address of the next instruction to be executed + 4
SPSR_fiq = CPSR
CPSR [4:0] = 0b10001 /* Enter FIQ mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [6] = 1 /* Disable fast interrupts */
CPSR [7] = 1 /* Disable interrupts */
CPSR [8] = 1 /* Disable imprecise aborts */
CPSR [9] = Secure EE-bit /* store value of secure Control Reg[25] */
CPSR[24] = 0 /* Clear J bit */
if high vectors configured then
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