ARM ARM1176JZF-S Technical Reference Manual page 594

Table 16-15 <addr_md_1cycle> and <addr_md_2cycle> LDR example instruction explanation (continued)
Example instruction
LDR <Rd>, [<Rn>, -<Rm>] (!)
LDR <Rd>, [Rm, -<Rm> <shf> <cns>] (!)
LDR <Rd>, [<Rn>], -<Rm>
LDR <Rd>, [<Rn>], -<Rm> <shf> <cns>
16.10.1 Base register update
ARM DDI 0301H
ID012310
The base register update for load or store instructions occurs in the ALU pipeline. To prevent an
interlock for back-to-back load or store instructions reusing the same base register, there is a
local forwarding path to recycle the updated base register around the ADD stage.
For example, the following instruction sequence take three cycles to execute:
LDR R5, [R2, #4]!
LDR R6, [R2, #0x10]!
LDR R7, [R2, #0x20]!
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Early Reg Comment
If negative register offset, or shift other than LSL #2 then
<Rm>
two-issue cycles.
<Rm>
<Rm>
<Rm>
Cycle Timings and Interlock Behavior
16-18