Cacheable Write-Through Or Noncacheable Stm6 To Word 0, 1, Or 2; Cacheable Write-Through Or Noncacheable Stm6 To Word 3, 4, 5, 6, Or 7; Cacheable Write-Through Or Noncacheable Stm7 To Word 0 Or 1 - ARM ARM1176JZF-S Technical Reference Manual

8.5.29 Cacheable Write-Through or Noncacheable STM6
Address[4:0]
, word 0
0x00
, word 1
0x04
, word 2
0x08
8.5.30 Cacheable Write-Through or Noncacheable STM7
Address[4:0]
0x00 , word 0
0x04 , word 1
ARM DDI 0301H
ID012310
Table 8-55 Cacheable Write-Through or Noncacheable STM5 to word 4, 5, 6, or 7
Table 8-56 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for STM6s to words 0 to 2 over the Data Read/Write Interface.
An STM6 to words 3 to 7 is split into two operations as shown in Table 8-57.
Table 8-56 Cacheable Write-Through or Noncacheable STM6 to word 0, 1, or 2
AWADDRR AWBURSTR
W W
Incr
0x00
Incr
0x04
Incr
0x08
Table 8-57 Cacheable Write-Through or Noncacheable STM6 to word 3, 4, 5, 6, or 7
Table 8-58 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for STM7s to words 0 or 1 over the Data Read/Write Interface.
An STM7 to words 2 to 7 is split into two operations as shown in Table 8-59 on page 8-32.
Table 8-58 Cacheable Write-Through or Noncacheable STM7 to word 0 or 1
AWADDRR AWBURSTR
W W
0x00 Incr
0x04 Incr
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Address[4:0] Operations
, word 5 STM3 to
0x14
, word 6 STM2 to
0x18
, word 7 STR to
0x1C
AWSIZERW AWLENRW
64-bit 3 data transfers
32-bit 6 data transfers
64-bit 3 data transfers
Address[4:0] Operations
0x0C , word 3 STM5 to
0x10 , word 4 STM4 to
0x14 , word 5 STM3 to
, word 6 STM2 to
0x18
, word 7 STR to
0x1C
AWSIZERW AWLENRW
32-bit 7 data transfers
32-bit 7 data transfers
Level Two Interface
+ STM2 to
0x14 0x00
+ STM3 to
0x18 0x00
+ STM4 to
0x1C 0x00
First WSTRBRW
b1111 1111
b1111 0000
b1111 1111
0x0C + STR to 0x00
0x10 + STM2 to 0x00
0x14 + STM3 to 0x00
+ STM4 to
0x18 0x00
+ STM5 to
0x1C 0x00
First WSTRBRW
b0000 1111
b1111 0000
8-31