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6.9.2
Alignment fault
6.9.3
Translation fault
6.9.4
Access bit fault
ARM DDI 0301H
ID012310
An alignment fault occurs if the processor has attempted to access a particular data memory size
at an address location that is not aligned with that size.
Operation of unaligned accesses on page 4-13 describes the conditions for generating
Alignment faults.
Alignment checks are performed with the MMU both enabled and disabled.
There are two types of translation fault:
Section
A section translation fault occurs if:
•
The TLB tries to perform a page table walk but the page table walk is
disabled by one of the PD0 or PD1 bits. For more details, see Hardware
page table translation on page 6-36.
•
The TLB fetches a first level translation table descriptor, and this first level
descriptor is invalid. This is the case when bits[1:0] of this descriptor are
b00 or b11.
Page
A page translation fault occurs if the TLB fetches a second-level translation table
descriptor and this descriptor is marked as invalid, bits [1:0] = b00.
When the Force AP bit, see c1, Control Register on page 3-44 bit [29], is set then AP[0]
indicates if there is an Access Bit Fault.
This bit is only taken into account when the MMU is in ARMv6 mode, that is XP=1, bit [23] in
the CP15 Control register.
In the configuration XP=1 and ForceAP=1, the OS uses only bits APX and AP[1] as Access
Permission bits, and AP[0] becomes an Access Bit, see Access permissions on page 6-11. The
Access Bit records recent TLB access to a page, or section, and the OS can use this to optimize
memory managements algorithms.
In the ARM1176JZF-S processor the Access Bit must be managed by the software.
Reading a page table entry into the TLB when the Access Bit is 0 causes an Access Bit fault.
This fault is readily distinguished from other faults that the TLB generates and this permits fast
setting of the Access Bit in software.
The processor can generate two kind of Access Bit faults:
•
Section Access Bit fault, when the Access Bit, AP[0], is contained in a first level
translation table descriptor
•
Page Access Bit fault, when the Access Bit, AP[0], is contained in a second level
translation table descriptor
The Force AP bit is banked in the Secure and Non-secure copies of the CP15 Control Register
for TrustZone support.
The Force AP and XP bits are expected to be static throughout operations.
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Memory Management Unit
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