Table 13-9 Breakpoint Value Registers, Bit Field Definition; Table 13-10 Processor Breakpoint Control Registers; Figure 13-6 Breakpoint Control Registers, Format - ARM ARM1176JZF-S Technical Reference Manual

13.3.8 CP14 c80-c85, Breakpoint Control Registers (BCR)
Binary address
Opcode_2
b101
ARM DDI 0301H
ID012310
Table 13-9 lists the bit field definitions for context ID and non context ID Breakpoint Value
Registers.
Context ID capable?
No
Yes
When a context ID capable BRP is set for IMVA comparison, BVR bits [1:0] are ignored.
These registers contain the necessary control bits for setting:
• breakpoints
• linked breakpoints.
Table 13-10 lists the Breakpoint Control Registers and that the processor implements.
Register
number
CRm
b0000-b0011 c80-c83
b0100-b0101 c84-c85
Figure 13-6 shows the format of the Breakpoint Control Registers.
31
UNP/SBZP
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Table 13-9 Breakpoint Value Registers, bit field definition

Bits Read/write attributes
[31:2] RW
[31:0] RW

Table 13-10 Processor Breakpoint Control Registers

CP14 debug register name
Breakpoint Control Registers 0-3
Breakpoint Control Registers 4-5
23 22 21 20 19 16 15 14
M E Linked BRP
Secure breakpoint match

Figure 13-6 Breakpoint Control Registers, format

Description
Breakpoint address
Breakpoint address or context ID
Abbreviation
BCR0-3
BCR4-5
13 9 8 5 4 3 2 1 0
Byte
UNP/
UNP/SBZP address
select
Debug
Context ID
capable?
No
Yes
S B
SBZ
13-17