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21.6.2
Single-precision source register locking
ARM DDI 0301H
ID012310
In full-compliance mode, the source scoreboard locks all source registers in the Issue stage of
the instruction. In RunFast mode, the source scoreboard locks the source registers for only
iterations 5, 6, 7, and 8. Table 21-1 summarizes source register locking in single-precision
operations.
LEN
b000
b001
b010
b011
b100
b101
b110
b111
For the following single-precision short vector instruction, the LEN field contains b100,
selecting a vector length of five iterations:
FADDS S8, S16, S24
The FADDS instruction performs the following operations:
FADDS S8, S16, S24
FADDS S9, S17, S25
FADDS S10, S18, S26
FADDS S11, S19, S27
FADDS S12, S20, S28
In full-compliance mode, the source scoreboard locks S16-S20 and S24-S28 in the Issue stage
of the instruction.
In RunFast mode, the source scoreboard locks only the fifth iteration source registers, S20 and
S28.
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Table 21-1 Single-precision source register locking
Source registers locked in Issue stage
Vector length
Full-compliance mode
1
Iteration 1 registers
2
Iteration 1-2 registers
3
Iteration 1-3 registers
4
Iteration 1-4 registers
5
Iteration 1-5 registers
6
Iteration 1-6 registers
7
Iteration 1-7 registers
8
Iteration 1-8 registers
VFP Instruction Execution
RunFast mode
-
-
-
-
Iteration 5 registers
Iteration 5-6 registers
Iteration 5-7 registers
Iteration 5-8 registers
21-8
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