Cacheable Write-Through Or Noncacheable Stm7 To Word 2, 3, 4, 5, 6 Or 7; Cacheable Write-Through Or Noncacheable Stm8 To Word 0; Cacheable Write-Through Or Noncacheable Stm8 To Word 1, 2, 3, 4, 5, 6, Or 7; Table 8-62 Cacheable Write-Through Or Noncacheable Stm9 - ARM ARM1176JZF-S Technical Reference Manual

8.5.31 Cacheable Write-Through or Noncacheable STM8
Address[4:0]
, word 0
0x00
8.5.32 Cacheable Write-Through or Noncacheable STM9
ARM DDI 0301H
ID012310
Table 8-59 Cacheable Write-Through or Noncacheable STM7 to word 2, 3, 4, 5, 6 or 7
Table 8-60 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for an STM8 to word 0 over the Data Read/Write Interface.
An STM8 to words 1 to 7 is split into two operations as shown in Table 8-61.
Table 8-60 Cacheable Write-Through or Noncacheable STM8 to word 0
AWADDRR AWBURSTR
W W
Incr
0x00
Table 8-61 Cacheable Write-Through or Noncacheable STM8 to word 1, 2, 3, 4, 5, 6, or 7
An STM9 over the Data Read/Write Interface is split into two operations as shown in
Table 8-62.
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Address[4:0]
, word 2
0x08
, word 3
0x0C
, word 4
0x10
, word 5
0x14
, word 6
0x18
, word 7
0x1C
AWSIZERW
64-bit
Address[4:0]
0x04 , word 1
0x08 , word 2
, word 3
0x0C
, word 4
0x10
, word 5
0x14
, word 6
0x18
, word 7
0x1C

Table 8-62 Cacheable Write-Through or Noncacheable STM9

Address[4:0]
0x00 , word 0
0x04 , word 1
, word 2
0x08
Level Two Interface
Operations
STM6 to + STR to
0x08
STM5 to + STM2 to
0x0C
STM4 to + STM3 to
0x10
STM3 to + STM4 to
0x14
STM2 to + STM5 to
0x18
STR to + STM6 to
0x1C
AWLENRW First WSTRBRW
4 data transfers b1111 1111
Operations
STM7 to 0x04 + STR to
STM6 to 0x08 + STM2 to
STM5 to + STM3 to
0x0C
STM4 to + STM4 to
0x10
STM3 to + STM5 to
0x14
STM2 to + STM6 to
0x18
STR to + STM7 to
0x1C
Operations
STM8 to 0x00 + STR to
STM7 to 0x04 + STM2 to
STM6 to + STM3 to
0x08
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
8-32