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21.1
About instruction execution
ARM DDI 0301H
ID012310
Features of the VFP11 implementation of the instruction pipelines include the following:
•
The FMXR, FMRX, and FMSTAT instructions stall in the VFP11 LS pipeline until all
currently executing instructions are completed. You can use these serializing instructions
to:
—
capture condition codes and exception status
—
modify the mode of operation of subsequent instructions
—
create an exception boundary.
See Serializing instructions on page 21-3.
•
Load or store instructions that cause a Data Abort exception restart after interrupt service.
LDM and STM instructions detect exceptional conditions after the first transfer and restart
after interrupt service if reissued.
See Interrupting the VFP11 coprocessor on page 21-4.
•
To reduce stall time, the VFP11 coprocessor forwards data:
—
from load instructions to CDP instructions
—
from CDP instructions to CDP instructions.
See Forwarding on page 21-5.
•
In full-compliance mode, the VFP11 coprocessor implements full data hazard and
resource hazard detection.
RunFast mode guarantees no instruction bouncing for applications that require less strict
hazard detection.
See Hazards on page 21-6 and Operation of the scoreboards on page 21-7.
•
The L/S, FMAC, and DS pipelines operate independently, enabling data transfer and CDP
operations to execute in parallel.
See Parallel execution on page 21-20.
Execution timing on page 21-22 describes VFP11 instruction throughput and latency.
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VFP Instruction Execution
21-2
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