ARM ARM1176JZF-S Technical Reference Manual page 496

Read/write
Bits
attributes
[15:14] RW
[13:9] SBZ
[8:5] RW
[4:3] RW
[2:1] RW
[0] RW
ARM DDI 0301H
ID012310
Table 13-16 Watchpoint Control Registers, bit field definitions (continued)
Reset
Description
value
- b00 = Watchpoint matches in Secure or Non-secure world.
b01 = Watchpoint only matches in Non-secure world.
b10 = Watchpoint only matches in Secure world.
b11 = Reserved.
- Reserved.
- Byte address select. The WVR is programmed with a word address. This field can be
used to program the watchpoint so it hits only if certain byte addresses are
accessed.b0000 = The watchpoint never hits
bxxx1= If the byte at address {WVR[31:2], b00}+0 is accessed, the watchpoint
hitsbxx1x = If the byte at address {WVR[31:2], b00}+1 is accessed, the watchpoint
hitsbx1xx = If the byte at address {WVR[31:2], b00}+2 is accessed, the watchpoint
hitsb1xxx = If the byte at address {WVR[31:2], b00}+3 is accessed, the watchpoint
hits.
Note
These are little-endian byte addresses. This ensures that a watchpoint is triggered
regardless of the way it is accessed.
For example, if a watchpoint is set on a certain byte in memory by doing WCR[8:5]
= b0001.
in legacy big-endian mode, B bit of CP15 c1 set.
R0, #x3
- Load/store access. The watchpoint can be conditioned to the type of access being
done:
b00 = Reserved
b01 = Load
b10 = Store
b11 = Either.
A SWP triggers on Load, Store, or Either. Load exclusive instructions, LDREX,
LDREXB, LDREXD, and LDREXH, trigger on Load or Either. Store exclusive
instructions, STREX, STREXB, STREXD, and STREXH, trigger on Store or Either,
whether it succeeded or not.
- Supervisor Access. The watchpoint can be conditioned to the privilege of the access
being done:
b00 = Reserved
b01 = Privileged
b10 = User
b11 = Either.
0 Watchpoint enable:
0 = Watchpoint disabled
1 = Watchpoint enabled.
In addition to the rules for breakpoint debug event generation, see CP14 c80-c85, Breakpoint
Control Registers (BCR) on page 13-17, the following rules apply to the processor for
watchpoint debug event generation:
• The update of a WVR or a WCR can take effect several instructions after the
corresponding MCR. It only guaranteed to have taken effect by the next IMB.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
it triggers the watchpoint in little-endian mode, as does
LDRB R0, #0x0
Debug
LDRB
13-22