ARM ARM1176JZF-S Technical Reference Manual page 758

VA
Vector operation
Victim
Virtual Address (VA)
Warm reset
Watchpoint
Way
WB
Word
Word-invariant
Write
Write-back (WB)
Write buffer
ARM DDI 0301H
ID012310
See Virtual Address.
A VFP coprocessor operation involving more than one destination register, perhaps involving
different source registers in the generation of the result for each destination.
See also Scalar operation.
A cache line, selected to be discarded to make room for a replacement cache line that is required
as a result of a cache miss. The way in which the victim is selected for eviction is
processor-specific. A victim is also known as a cast out.
The MMU uses its page tables to translate a Virtual Address into a Physical Address. The
processor executes code at the Virtual Address, which might be located elsewhere in physical
memory.
See also Fast Context Switch Extension, Modified Virtual Address, and Physical Address.
Also known as a core reset. Initializes the majority of the processor excluding the debug
controller and debug logic. This type of reset is useful if you are using the debugging features
of a processor.
A watchpoint is a mechanism provided by debuggers to halt program execution when the data
contained by a particular memory address is changed. Watchpoints are inserted by the
programmer to enable inspection of register contents, memory locations, and variable values
when memory is written to test that the program is operating correctly. Watchpoints are removed
after the program is successfully tested. See also Breakpoint.
See Cache way.
See Write-back.
A 32-bit data item.
In a word-invariant system, the address of each byte of memory changes when switching
between little-endian and big-endian operation, in such a way that the byte with address A in
one endianness has address A EOR 3 in the other endianness. As a result, each aligned word of
memory always consists of the same four bytes of memory in the same order, regardless of
endianness. The change of endianness occurs because of the change to the byte addresses, not
because the bytes are rearranged. The ARM architecture supports word-invariant systems in
ARMv3 and later versions. When word-invariant support is selected, the behavior of load or
store instructions that are given unaligned addresses is instruction-specific, and is in general not
the expected behavior for an unaligned access. It is recommended that word-invariant systems
should use the endianness that produces the required byte addresses at all times, apart possibly
from very early in their reset handlers before they have set up the endianness, and that this early
part of the reset handler should use only aligned word memory accesses.
See also Byte-invariant.
Writes are defined as operations that have the semantics of a store. That is, the ARM instructions
SRS, STM, STRD, STC, STRT, STRH, STRB, STRBT, STREX, SWP, and SWPB, and the
Thumb instructions STM, STR, STRH, STRB, and PUSH. Java instructions that are accelerated
by hardware can cause a number of writes to occur, according to the state of the Java stack and
the implementation of the Java hardware acceleration.
In a write-back cache, data is only written to main memory when it is forced out of the cache on
line replacement following a cache miss. Otherwise, writes by the processor only update the
cache. It is also known as copyback.
A block of high-speed memory, arranged as a FIFO buffer, between the data cache and main
memory, whose purpose is to optimize stores to main memory.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Glossary
Glossary-19