Typical Pipeline Operations; Figure 1-3 Typical Operations In Pipeline Stages; Figure 1-4 Typical Alu Operation - ARM ARM1176JZF-S Technical Reference Manual

1.9

Typical pipeline operations

Fe1
1st fetch
stage
Fe1
1st fetch
stage
ARM DDI 0301H
ID012310
Figure 1-3 shows all the operations in each of the pipeline stages in the ALU pipeline, the
load/store pipeline, and the HUM buffers.
Fe2 De
2nd fetch Instruction read and
stage decode instruction
Common decode pipeline
Figure 1-4 shows a typical ALU data processing instruction. The processor does not use the
load/store pipeline or the HUM buffer.
Fe2 De
2nd fetch Instruction read and
stage decode instruction
Common decode pipeline
Figure 1-5 on page 1-29 shows a typical multiply operation. The MUL instruction can loop in
the MAC1 stage until it has passed through the first part of the multiplier array enough times.
The MUL instruction progresses to MAC2 and MAC3 where it passes through the second half
of the array once to produce the final result.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Ex1 Ex2
Sh ALU
Calculate
Shifter
writeback
Iss
operation
value
Register
MAC1 MAC2
issue
1st 2nd
multiply multiply
stage stage
ADD DC1
First stage
Data
of data
address
cache
calculation
access
Load miss
waits

Figure 1-3 Typical operations in pipeline stages

Ex1 Ex2
Sh ALU
Calculate
Shifter
writeback
Iss
operation
value
Register
MAC1 MAC2
issue
Not used Not used
ADD DC1
Not used Not used
Not used
Introduction
Ex3
Sat
Saturation
WBex
Base
register
MAC3
writeback
3rd
multiply
stage
DC2 WBls
Second
Load/store
stage of Writeback
data cache from LSU
access
Hit under
Ex3
Sat
Saturation
WBex
Base
register
MAC3
writeback
Not used
DC2 WBls
Load/store
Not used Not used
Hit under

Figure 1-4 Typical ALU operation

ALU
pipeline
Multiply
pipeline
pipeline
miss
ALU
pipeline
Multiply
pipeline
pipeline
miss
1-28