Figure 9-3 Processor Clocks With Iem; Figure 9-4 Processor Synchronization With Iem - ARM ARM1176JZF-S Technical Reference Manual

VIC interface
CLKIN
Clock enables
IEM
register
slices
ACLK clocks
Clock
SYNCMODEREQ
SYNCMODEACK
ARM DDI 0301H
ID012310
Processor
Instruction
level 2
interface
CLK
VCoreSliceI
Level shift and
clamp
VSoCSliceI
Synchronization with IEM
When the core runs at maximum performance, the two clocks for the IEM Register Slice are
synchronous. At this point, when frequency and voltage changes have taken effect, the IEM
Register Slice can be bypassed. This removes all the latency that the synchronizers introduce.
The synchronization interface is a simple request and acknowledge system. Figure 9-4 shows
the processor synchronization with such a system.
FIFOs drain
Normal FIFO operation
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RAMs
Level shift and clamp
Core
Data read/
DMA level
write level
2 interface
2 interface
CLK
VCoreSliceRW VCoreSliceD
Level shift and Level shift and
clamp clamp
VSoCSliceRW VSoCSliceD
Level 2
FIFO multiplexed out
FIFOs all empty
FIFOs closed to new data

Figure 9-4 Processor synchronization with IEM

Clocking and Resets
Peripheral
level 2
interface
CLK CLK
VCoreSliceP
Level shift and
clamp
VSoCSliceP

Figure 9-3 Processor clocks with IEM

Synchronization
Normal FIFO operation
Debug
interface
over
9-6