Figure 14-14 Behavior Of The Itrsel Ir Instruction - ARM ARM1176JZF-S Technical Reference Manual

14.7.3 Using the ITRsel IR instruction
ARM DDI 0301H
ID012310
7. Scan_N into the IR.
8. 4 into the SCREG.
9. EXTEST into the IR.
10. Scan the
MCR p14,0,R0,c0,c5,0
11. Go through the Run-Test/Idle state of the DBGTAPSM.
12. Scan_N into the IR.
13. 5 into the SCREG.
14. INTEST into the IR.
15. Scan out 34 bits. The 33rd bit indicates if the instruction has completed. If the bit is clear,
repeat this step again.
16. The least significant 32 bits hold the contents of R0.
When the ITRsel instruction is loaded into the IR, at the Update-IR state, the DBGTAP
controller behaves as if EXTEST and scan chain 4 are selected, but SCREG retains its value. It
can be used to speed up certain debug sequences.
Figure 14-14 shows the effect of the ITRsel IR instruction.
Consider for example the preceding sequence to store out the contents of ARM register R0. This
is the same sequence using the ITRsel instruction:
1. Scan_N into the IR.
2. 1 into the SCREG.
3. INTEST into the IR.
4. Scan out the contents of the DSCR. This action clears the sticky precise Data Abort and
sticky imprecise Data Abort flags.
5. EXTEST into the IR.
6. Scan in the previously read value with the DSCR[13] execute ARM instruction enable bit
set.
7. Scan_N into the IR.
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instruction into the ITR.
EXTEST
=ITRSEL? Yes

Figure 14-14 Behavior of the ITRsel IR instruction

Debug Test Access Port
IR SCREG
4
1 0 1 0
Current IR Current
instruction scan chain
14-22