Table 3-47 Operation Of The Fw And Fiq Bits; Table 3-48 Operation Of The Aw And Ea Bits - ARM ARM1176JZF-S Technical Reference Manual

Bits
[3]
[2]
[1]
[0]
AW EA
1 0
0 1
1 1
0 0
ARM DDI 0301H
ID012310
Table 3-46 Secure Configuration Register bit functions (continued)
Field name Function
EA Determines External Abort behavior for Secure and Non-secure worlds:
0 = Branch to abort mode on an External Abort exception, reset value
1 = Branch to Secure Monitor mode on an External Abort exception.
FIQ Determines FIQ behavior for Secure and Non-secure worlds:
0 = Branch to FIQ mode on an FIQ exception, reset value
1 = Branch to Secure Monitor mode on an FIQ exception.
IRQ Determines IRQ behavior for Secure and Non-secure worlds:
0 = Branch to IRQ mode on an IRQ exception, reset value
1 = Branch to Secure Monitor mode on an IRQ exception.
NS bit Defines the world for the processor:
0 = Secure, reset value
1 = Non-secure.
Note
When the core runs in Secure Monitor mode the state is considered Secure regardless of the state
of the NS bit. However, Monitor mode code can access nonsecure banked copies of registers if
the NS bit is set to 1. See the ARM Architecture Reference Manual for information on the effect
of the Security Extensions on the CP15 registers.
The permutations of the bits in the Secure Configuration Register have certain security
implications. Table 3-47 lists the results for combinations of the FW and FIQ bits.
FW FIQ Function
1 0 FIQs handled locally.
0 1 FIQs can be configured to give deterministic Secure interrupts.
1 1 Non-secure world able to make denial of service attack, avoid use of this function.
0 0 Avoid because the core might enter an infinite loop for Non-secure FIQ.
Table 3-48 lists the results for combinations of the AW and EA bits.
Function
Aborts handled locally.
All external aborts trapped to Secure Monitor.
All external imprecise data aborts trapped to Secure Monitor but the Non-secure world can hide Secure
aborts from the Secure Monitor, avoid use of this function.
Avoid because the core can unexpectedly enter an abort mode in the Non-secure world.
For more details on the use of Secure Monitor mode, see The NS bit and Secure Monitor mode
on page 2-4.
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System Control Coprocessor

Table 3-47 Operation of the FW and FIQ bits

Table 3-48 Operation of the AW and EA bits

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