Table 21-4 Double-Precision Source Register Clearing For One-Cycle Instructions; Table 21-5 Double-Precision Source Register Clearing For Two-Cycle Instructions - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
Instructions with one-cycle throughput
In full-compliance mode, the source scoreboard clears the source registers of each iteration in
the Execute 1 stage of the iteration. In RunFast mode, the source registers for only iterations 3
and 4 are locked, and the source scoreboard begins clearing them in the first Execute 1 cycle of
the instruction. Table 21-4 summarizes source register clearing for double-precision one-cycle
instructions such as FADDD and FABSD.

Table 21-4 Double-precision source register clearing for one-cycle instructions

Execute 1 cycle
1
2
3
4
For the following one-cycle, double-precision short vector instruction, the LEN field contains
b011, selecting a vector length of four iterations:
FADDD D4, D8, D12
The FADDD performs the following operations:
FADDD D4, D8, D12
FADDD D5, D9, D13
FADDD D6, D10, D14
FADDD D7, D11, D15
In full-compliance mode, the source scoreboard clears the source registers of each iteration in
the Execute 1 cycle of the iteration.
In RunFast mode, the source scoreboard locks only the third iteration source registers, D10 and
D14, and the fourth iteration source registers, D11 and D15. It clears D10 and D14 in the first
Execute 1 cycle of the instruction and clears D11 and D15 in the second Execute 1 cycle.
Instructions with two-cycle throughput
In full-compliance mode, the source scoreboard clears the source registers of each iteration in
the first Execute 1 cycle of the iteration. In RunFast mode, the source registers for only iterations
3 and 4 are locked, and the source scoreboard begins clearing them in the first Execute 1 cycle
of the instruction. Table 21-5 summarizes source register clearing for double-precision
two-cycle instructions such as FMULD and FMACD.

Table 21-5 Double-precision source register clearing for two-cycle instructions

Execute 1 cycle
1
2
3
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Source registers cleared in Execute 1 stage of each iteration
Full-compliance mode
Iteration 1 registers
Iteration 2 registers
Iteration 3 registers
Iteration 4 registers
Source registers cleared in Execute 1 stage of each iteration
Full-compliance mode
Iteration 1 registers
-
Iteration 2 registers
VFP Instruction Execution
RunFast mode
Iteration 3 registers
Iteration 4 registers
-
-
RunFast mode
Iteration 3 registers
-
Iteration 4 registers
21-11