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Bits
Reference name
DDImpAbort
[3]
DDFail
[2]
DDSlot
[1:0]
15.1.5
Pipeline advance interface
15.1.6
Coprocessor interface
ARM DDI 0301H
ID012310
Table 15-6 lists the data value interface signals.
Signal name
Description
ETMDDCTL[3:0]
Data value interface control signals
ETMDD[63:0]
Contains the data for a load, store, MRC, or MCR instruction
Table 15-7 lists the ETMDDCTL[3:0] signals.
Description
Imprecise Data Aborts on this slot. Data is ignored.
Store Exclusive data write failed.
Slot occupied by data item. b00 indicates that no slot is in use this cycle.
This is kept b00 when the ETM is powered down.
There are three points in the processor pipeline where signals are produced for the ETM. These
signals must be realigned by the ETM, so pipeline advance signals are provided.
The pipeline advance signals indicate when a new instruction enters pipeline stages Ex3, Ex2,
and ADD, see Typical pipeline operations on page 1-28.
Table 15-8 lists the ETMPADV[2:0] pipeline advance interface signals
Bits
Reference name
PAEx3
[2]
a
PAEx2
[1]
a
PAAdd
[0]
a
a. This is kept LOW when the ETM is powered down.
The pipeline advance signals present in other interfaces are:
IAValid
Instruction entered WBEx.
DASlot != 00
Data transfer entered DC1.
DDSlot != 00
Data transfer entered WBls.
This interface enables an ETM to monitor a sub-set of CP14 and CP15 operations. Rather than
using the external coprocessor interface, the core provides a dedicated, cut-down coprocessor
interface similar to that used by the debug logic.
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Table 15-6 Data value interface signals
Description
Instruction entered Ex3
Instruction entered Ex2
Instruction entered Ex1 and load/store ADD stage
Trace Interface Port
Qualified by
-
DDSlot != 00
Table 15-7 ETMDDCTL[3:0]
Qualified by
DDSlot != 00
DDSlot != 00
None
Table 15-8 ETMPADV[2:0]
Qualified by
-
-
-
15-6
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