Resource Hazards - ARM ARM1176JZF-S Technical Reference Manual

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21.9

Resource hazards

21.9.1
Load multiple-load-CDP resource hazard example
ARM DDI 0301H
ID012310
A resource hazard exists when the pipeline required for an instruction is unavailable because of
a prior instruction. VFP11 resource stalls are possible in the following cases:
A data transfer operation following an incomplete data transfer operation can cause a
resource stall. The ARM11 processor can stall each data transfer because of unavailable
data caused by memory latency or a cache miss, increasing the latency of the data transfer
instruction and stalling any following data transfer instructions.
An arithmetic operation following either a short vector arithmetic operation or a
double-precision multiply or multiply and accumulate operation can cause a resource
stall. The latency for a double-precision multiply or multiply and accumulate operation is
two cycles, causing a single-cycle stall for an arithmetic operation that immediately
follows.
A single-precision divide or square root operation stalls subsequent DS operations for 15
cycles. A double-precision divide or square root operation stalls subsequent DS
operations for 29 cycles.
A short vector divide or square root operation requires the FMAC pipeline for the first
cycle of each iteration and stalls any following CDP operation. The following CDP
operation stalls until the final iteration of the short vector divide or square root operation
completes the Execute 1 stage.
The LS pipeline is separate from the FMAC and DS pipelines. No resource hazards exist
between data transfer instructions and arithmetic instructions.
The sections that follow give examples of resource hazards:
Load multiple-load-CDP resource hazard example
Load multiple-short vector CDP resource hazard example on page 21-18
Short vector CDP-CDP resource hazard example on page 21-18.
In Example 21-10, the FLDM is executing two transfers to the VFP11 coprocessor. The FLDS
is stalled behind the FLDM until the FLDM enters the final Execute cycle. The FADDS is stalled
for one cycle until the FLDS begins execution.
FLDM [R2], {S8-S10}
FLDS [R4], S16
FADDS S2, S3, S4
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Example 21-10 FLDM-FLDS-FADDS resource hazard
VFP Instruction Execution
21-17

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