Figure 13-5 Vector Catch Register Format - ARM ARM1176JZF-S Technical Reference Manual

13.3.6 CP14 c7, Vector Catch Register (VCR)
31 30 29 28 27 26 25 24
FIQ
IRQ
Reserved
Data abort
Prefetch abort
Undefined Instruction
Non-secure world
ARM DDI 0301H
ID012310
A write to this register sets the WFAR to the value of the data written. This is useful for a
debugger to restore the value of the WFAR.
The processor supports efficient exception vector catching. This is controlled by the VCR, as
Figure 13-5 shows.
Reserved,
DNM / RAZ
SVC
If one of the bits in this register is set and the corresponding vector is committed for execution,
then a Debug exception or Debug state entry might be generated, depending on the value of the
DSCR[15:14] bits. See Behavior of the processor on debug events on page 13-33. Under this
model, any kind of fetch of an exception vector can trigger a vector catch, not only the ones
because of exception entries.
Vector catches related to bits[15:0] are only triggered by fetches in a Secure world. Catches
related to bits [31:25] are only triggered in the Non-secure world.
There are three groups of bits one each to catch exceptions relative to the three vector base
address registers for Non-secure, Secure and Secure Monitor modes.
The update of the VCR might occur several instruction after the corresponding MCR
instruction. It only takes effect by the next Instruction Memory Barrier (IMB).
Bits 29, [24:16], 13, [9:8] and bit 5 are reserved.
Table 13-6 on page 13-14 lists the bit field definitions for the Vector Catch Register. In
Table 13-6 on page 13-14, SBA means Secure Base Address, NSBA means Non-secure Base
Address, MBA means Monitor Base Address.
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16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIQ
IRQ
Reserved
Data abort
Prefetch abort
SMC
Reserved
Secure world,
Secure Monitor entry

Figure 13-5 Vector Catch Register format

Debug
Reset
Undefined
Instruction
SVC
Prefetch abort
Data abort
Reserved
IRQ
FIQ
Secure world
13-13