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13.11 Debug communications channel
ARM DDI 0301H
ID012310
There are two ways that a DBGTAP debugger can send data to or receive data from the core:
•
The debug communications channel, when the core is not in Debug state. It is defined as
the set of resources used for communicating between the DBGTAP debugger and a piece
of software running on the core.
•
The mechanism for forcing the core to execute ARM instructions, when the core is in
Debug state. For details see Executing instructions in Debug state on page 14-21.
At the core side, the debug communications channel resources are:
•
CP14 Debug Register c5, DTR. Data coming from a DBGTAP debugger can be read by
an MRC or STC instruction addressed to this register. The core can write to this register
any data intended for the DBGTAP debugger, using an MCR or LDC instruction. Because
the DTR comprises both a read, rDTR, and a write portion, wDTR, a data item written by
the core can be held in this register at the same time as one written by the DBGTAP
debugger.
•
Some flags and control bits of CP14 Debug Register c1, DSCR:
—
User mode access to comms channel disable, DSCR[12]. If this bit is set, only
privileged software is able to access the debug communications channel. That is,
access the DSCR and the DTR.
—
wDTRfull flag, DSCR bit 29. When clear, this flag indicates to the core that the
wDTR is ready to receive data. It is automatically cleared on reads of the wDTR by
the DBGTAP debugger, and is set on writes by the core to the same register. If this
bit is set and the core attempts to write to the wDTR, the register contents are
overwritten and the wDTRfull flag remains set.
—
rDTRfull flag, DSCR bit 30. When set, this flag indicates to the core that there is
data available to read at the rDTR. It is automatically set on writes to the rDTR by
the DBGTAP debugger, and is cleared on reads by the core of the same register.
Monitor debug-mode debugging on page 14-42 describes the DBGTAP debugger side of the
debug communications channel.
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