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Read/write
Bits
attributes
[31:28]
R
WRP
[27: 24]
R
BRP
[23: 20]
R
Context
[19:16]
R
Version
[15:12]
R
[11:8]
UNP/SBZP
[7: 4]
R
Variant
[3: 0]
R
Revision
13.3.3
CP14 c1, Debug Status and Control Register (DSCR)
ARM DDI 0301H
ID012310
•
the value of DIDR[7:0] is determined by fields in the CP15 c0 Main ID Register, as
described in the field descriptions in Table 13-3.
Table 13-3 lists the bit field definitions for the Debug ID Register.
Description
Number of Watchpoint Register Pairs:
b0000 = 1 WRP
b0001 = 2 WRPs
...
b1111 = 16 WRPs.
For the ARM1176JZF-S processor these bits are b0001 (2 WRPs).
Number of Breakpoint Register Pairs:
b0000 = Reserved. The minimum number of BRPs is 2.
b0001 = 2 BRPs
b0010 = 3 BRPs
...
b1111 = 16 BRPs.
For the ARM1176JZF-S processor these bits are b0101 (6 BRPs).
Number of Breakpoint Register Pairs with context ID comparison capability:
b0000 = 1 BRP has context ID comparison capability
b0001 = 2 BRPs have context ID comparison capability
...
b1111 = 16 BRPs have context ID comparison capability.
For the ARM1176JZF-S processor these bits are b0001 (2 BRPs).
Debug architecture version.
Debug architecture revision 0x1 denotes TrustZone features
Reserved.
Implementation-defined variant number, incremented on major revisions of the product.
This field is identical to bits [23:20] of the CP15 c0 Main ID Register, see c0, Main ID
Register on page 3-20.
Implementation-defined revision number, incremented on minor revisions of the product.
This field is identical to bits [3:0] of the CP15 c0 Main ID Register, see c0, Main ID Register
on page 3-20.
The reason for duplicating the Variant and Revision fields here is that the Debug ID Register is
accessible through scan chain 0. This enables an external debugger to determine the variant and
revision numbers without stopping the core.
The Debug Status and Control Register contains status and configuration information about the
state of the debug system. Figure 13-3 on page 13-8 shows the format of the Debug Status and
Control Register.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Table 13-3 Debug ID Register bit field definition
denotes v6.1
0x2
Debug
13-7
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