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14.7.8
Transferring data in Debug state
ARM DDI 0301H
ID012310
5.
Now the data has been written into the rDTR. Go to step 4 again to send in more data.
When the core is in Debug state, the DBGTAP debugger can transfer data in and out of the core
using the instruction execution facilities that Executing instructions in Debug state on
page 14-21 describes in addition to scan chain 5. You must ensure that the DSCR[13] execute
ARM instruction enable bit is set for the instruction execution mechanism to work. When it is
set, the interface for the DBGTAP debugger consists of the following:
•
Scan chain 4. See Scan chain 4, instruction transfer register (ITR) on page 14-13. It is
used for loading an instruction and for monitoring the status of the execution:
ITR
InstCompl flag
•
Scan chain 5. See Scan chain 5 on page 14-15. It is used for writing in or reading out the
data and for monitoring the state of the execution:
rDTR
wDTR
InstCompl flag
•
Some flags and control bits at CP14 debug register c1, DSCR:
DSCR[13]
Sticky precise Data Abort flag
Sticky imprecise Data Abort flag
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When the DBGTAPSM goes through the Update-DR state with
EXTEST and scan chain 4 selected, and the Ready flag set, the ITR
is loaded with the least significant 32 bits of the scan chain.
When clear, this flag indicates to the DBGTAP debugger that the last
issued instruction has not yet completed execution. While Ready,
captured version of InstCompl, is clear, no updates of the ITR and
the rDTR occur and the instruction execution mechanism is
disabled. No instruction is issued when going through
Run-Test/Idle.
When the DBGTAPSM goes through the Update-DR state with
EXTEST and scan chain 5 selected, and the Ready flag set, the
contents of the Data field are loaded into the rDTR.
When the DBGTAPSM goes through the Capture-DR state with
INTEST or EXTEST selected, the contents of the wDTR are loaded
into the Data field of the scan chain.
When clear, this flag indicates to the DBGTAP debugger that the last
issued instruction has not yet completed execution. While Ready,
captured version of InstCompl, is clear, no updates of the ITR and
the rDTR occur and the instruction execution mechanism is
disabled. No instruction is issued when going through
Run-Test/Idle.
Execute ARM instruction enable bit. This bit must be set for the
instruction execution mechanism to work.
DSCR[6]. When set, this flag indicates to the DBGTAP debugger
that a precise Data Abort occurred while executing an instruction in
Debug state. While this bit is set, the instruction execution
mechanism is disabled. When this flag is set InstCompl stays HIGH,
and additional attempts to execute an instruction appear to succeed
but do not execute.
DSCR[7]. When set, this flag indicates to the DBGTAP debugger
that an imprecise Data Abort occurred while executing an
instruction in Debug state. This flag does not disable the Debug state
instruction execution.
Debug Test Access Port
14-25
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