Table 3-141 Results Of Access To The Count Register 1; Table 3-142 System Validation Counter Register Operations - ARM ARM1176JZF-S Technical Reference Manual

V bit
0
1
3.2.55 c15, System Validation Counter Register
ARM DDI 0301H
ID012310
Access to the Count Register 1 in User mode depends on the V bit, see c15, Secure User and
Non-secure Access Validation Control Register on page 3-132. The Count Register 1 is always
accessible in Privileged modes. Table 3-141 lists the results of attempted access for each mode.
Secure Privileged
Read Write
Data Data
Data Data
To access Count Register 1 read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c15
• CRm set to c12
• Opcode_2 set to 3.
For example:
MRC p15, 0, <Rd>, c15, c12, 3
MCR p15, 0, <Rd>, c15, c12, 3
The value in Count Register 1 is 0 at Reset.
You can use the Performance Monitor Control Register to set Count Register 1 to zero.
The purpose of the System Validation Counter Register is to count core clock cycles to trigger
a system validation event.
The System Validation Counter Register is:
• in CP15 c15
• a 32 bit read/write register common to the Secure and Non-secure worlds
• accessible in User and Privileged modes.
The System Validation Counter Register consists of one 32-bit register that performs four
functions. Table 3-142 lists the arrangement of the functions in this group. The reset value is 0.
CRn Opcode_1
c15 0
The reset, interrupt, and fast interrupt counters are 32-bits wide. The external debug request
counter is 6 bits wide. Figure 3-74 on page 3-141 shows the arrangement of bits for the external
debug request counter.
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Table 3-141 Results of access to the Count Register 1

Non-secure Privileged
Read Write
Data Data
Data Data
; Read Count Register 1
; Write Count Register 1

Table 3-142 System validation counter register operations

CRm Opcode_2
c12 1
2
3
7
System Control Coprocessor
User
Read Write
Undefined exception Undefined exception
Data Data
R/W Operation
R/W Reset counter
R/W Interrupt counter
R/W Fast interrupt counter
W External debug request counter
3-140