Table 22-2 Exceptional Short Vector Fadds With A Fadds In The Pretrigger Slot - ARM ARM1176JZF-S Technical Reference Manual

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Instruction
FADDS S24, S26, S28
FADDS S3, S4, S5
FMULS S12, S16, S16
ARM DDI 0301H
ID012310
UFC
1
Exception detected is a potential underflow.
OFC
0
IOC
0
The FPINST register contains the FMULD instruction with the following fields modified to
reflect the register address of the third iteration.
Fd/D
1010/0
Fm/M
1010/0
Fn/N
1110/0
The FPINST2 register contains invalid data.
In Example 22-2, the first FADDS is a short vector operation with b001 in the LEN field for a
vector length of two iterations and b00 in the STRIDE field for a vector stride of one. A potential
Invalid Operation exception is detected in the second iteration. The second FADDS progresses
to the Execute 1 stage and is captured in the FPINST2 register with the condition field changed
to AL, the FP2V flag set, and is not the trigger instruction. The FMULS is the trigger instruction
and bounces in cycle 6. It can be retried after exception processing.
Example 22-2 Exceptional short-vector FADDS with a FADDS in the pretrigger slot
FADDS S24, S26, S28
FADDS S3, S4, S5
FMULS S12, S16, S16
Table 22-2 lists the pipeline stages for Example 22-2.

Table 22-2 Exceptional short vector FADDS with a FADDS in the pretrigger slot

Instruction cycle number
1
2
3
D
I
E1
-
D
D
-
-
-
After exception processing begins, the FPEXC register fields contains the following:
EX
1
The VFP11 coprocessor is in the exceptional state.
EN
1
FP2V
1
FPINST2 contains a valid instruction.
VECITR
111
No iterations remaining after exceptional iteration.
INV
0
UFC
0
OFC
0
IOC
1
Exception detected is a potential invalid operation.
The FPINST register contains the FADDS instruction with the following fields modified to
reflect the register address of the second iteration:
Fd/D
1100/1
Destination is of the second exceptional iteration is S25.
Fn/N
1101/1
Fn source is of the second exceptional iteration is S27.
Fm/M
1110/1
Fm source is of the second exceptional iteration is S29.
The FPINST2 register contains the instruction word for the second FADDS with the condition
field changed to AL.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Destination of the third exceptional iteration is D10.
Fm source of the third exceptional iteration is D10.
Fn source of the third exceptional iteration is D14.
; Vector single-precision add of length 2
; Scalar single-precision add
; Short vector single-precision multiply
4
5
6
7
8
E1
E2
-
-
-
I
E1
-
-
-
D
I
*
-
-
VFP Exception Handling
9
10
11
12
13
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
14
15
16
-
-
-
-
-
-
-
-
-
22-10

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