Table 3-138 Results Of Access To The Performance Monitor Control Register - ARM ARM1176JZF-S Technical Reference Manual

V bit
0
1
3.2.52 c15, Cycle Counter Register
ARM DDI 0301H
ID012310
Access to the Performance Monitor Control Register in User mode depends on the V bit, see
c15, Secure User and Non-secure Access Validation Control Register on page 3-132. The
Performance Monitor Control Register is always accessible in Privileged modes. Table 3-138
lists the results of attempted access for each mode.

Table 3-138 Results of access to the Performance Monitor Control Register

Secure Privileged
Read Write
Data Data
Data Data
To access the Performance Monitor Control Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c15
• CRm set to c12
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c15, c12, 0
MCR p15, 0, <Rd>, c15, c12, 0
If this unit generates an interrupt, the processor asserts the pin nPMUIRQ. You can route this
pin to an external interrupt controller for prioritization and masking. This is the only mechanism
that signals this interrupt to the core. When asserted, this interrupt can only be cleared if bit 0 of
the Performance Monitor Control Register is high.
There is a delay of three cycles between an enable of the counter and the start of the event
counter. The information used to count events is taken from various pipeline stages. This means
that the absolute counts recorded might vary because of pipeline effects. This has negligible
effect except in cases where the counters are enabled for a very short time.
In addition to the two counters within the processor, most of the events that Table 3-137 on
page 3-135 lists are available on an external bus, EVNTBUS. You can connect this bus to the
ETM unit or other external trace hardware to enable the events to be monitored. If you do not
want this functionality, set the X bit in the Performance Monitor Control Register to 0. In Debug
state, the EVNTBUS is masked to zero.
The purpose of the Cycle Counter Register is to count the core clock cycles.
The Cycle Counter Register:
• is in CP15 c15
• is a 32-bit read/write register common to Secure and Non-secure worlds
• counts up and can trigger an interrupt on overflow.
The Cycle Counter Register bits[31:0] contain the count value. The reset value is 0.
You can use this register in conjunction with the Performance Monitor Control Register and the
two Counter Registers to provide a variety of useful metrics that enable you to optimize system
performance.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Non-secure Privileged
Read Write
Data Data
Data Data
; Read Performance Monitor Control Register
; Write Performance Monitor Control Register
System Control Coprocessor
User
Read Write
Undefined exception Undefined exception
Data Data
3-137