ARM ARM1176JZF-S Technical Reference Manual page 136

Function
Cache control and
configuration
TCM control and
configuration
Cache Master
Valid
DMA control
System
performance
monitor
ARM DDI 0301H
ID012310
Table 3-1 System control coprocessor register functions (continued)
Register/operation
Cache Type
Cache Operations
Data Cache Lockdown
Instruction Cache Lockdown
Cache Behavior Override
TCM Status
Data TCM Region
Instruction TCM Region
Data TCM Non-secure Access
Control
Instruction TCM Non-secure Access
Control
TCM Selection
Instruction Cache Master Valid
Data Cache Master Valid
DMA Identification and Status
DMA User Accessibility
DMA Channel Number
DMA enable
DMA Control
DMA Internal Start Address
DMA External Start Address
DMA Internal End Address
DMA Channel Status
DMA Context ID
Performance Monitor Control
Cycle Counter
Count Register 0
Count Register 1
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Reference to description
c0, Cache Type Register on page 3-21
c7, Cache operations on page 3-69
c9, Data and instruction cache lockdown registers on
page 3-87
c9, Data and instruction cache lockdown registers on
page 3-87
c9, Cache Behavior Override Register on page 3-97
c0, TCM Status Register on page 3-24
c9, Data TCM Region Register on page 3-89
c9, Instruction TCM Region Register on page 3-91
c9, Data TCM Non-secure Control Access Register on
page 3-93
c9, Instruction TCM Non-secure Control Access Register on
page 3-94
c9, TCM Selection Register on page 3-96
c15, Instruction Cache Master Valid Register on page 3-147
c15, Data Cache Master Valid Register on page 3-148
c11, DMA identification and status registers on page 3-106
c11, DMA User Accessibility Register on page 3-107
c11, DMA Channel Number Register on page 3-109
c11, DMA enable registers on page 3-110
c11, DMA Control Register on page 3-112
c11, DMA Internal Start Address Register on page 3-114
c11, DMA External Start Address Register on page 3-115
c11, DMA Internal End Address Register on page 3-116
c11, DMA Channel Status Register on page 3-117
c11, DMA Context ID Register on page 3-120
c15, Performance Monitor Control Register on page 3-133
c15, Cycle Counter Register on page 3-137
c15, Count Register 0 on page 3-138
c15, Count Register 1 on page 3-139
System Control Coprocessor
3-4