ARM Cortex-M3 DesignStart Manuals

Manuals and User Guides for ARM Cortex-M3 DesignStart. We have 3 ARM Cortex-M3 DesignStart manuals available for free PDF download: Technical Reference Manual, User Manual

ARM Cortex-M3 DesignStart Technical Reference Manual (410 pages)

r2p0

Brand: ARM | Category: Computer Hardware | Size: 2 MB

Table of Contents
5
Preface

20
- About this Book
  20
- Key to Timing Diagram Conventions
  23
- Feedback
  25
Chapter 1 Introduction

28
- About the Processor
  28
- Components, Hierarchy, and Implementation
  30
- Figure 1-1 Cortex-M3 Block Diagram
  31
- Table
  37
- Execution Pipeline Stages
  38
- Figure 1-2 Cortex-M3 Pipeline Stages
  38
- Prefetch Unit
  40
- Branch Target Forwarding
  41
- Store Buffers
  44
- Product Revisions
  45
- About the DP
  46
Chapter 2 Programmer's Model

50
Chapter 3 System Control

73
Chapter 4 Memory Map

89
- About the Memory Map
  90
- Figure 4-1 Processor Memory Map
  90
- Table 4-1 Memory Interfaces
  91
- Table 4-2 Memory Region Permissions
  92
- Bit-Banding
  93
- Figure 4-2 Bit-Band Mapping
  94
- ROM Memory Table
  95
- Table 4-3 ROM Table
  95
Chapter 5 Exceptions

98
- About the Exception Model
  98
- Exception Types
  100
- Table 5-1 Exception Types
  100
- Exception Priority
  102
- Table 5-2 Priority-Based Actions of Exceptions
  102
- Table 5-3 Priority Grouping
  104
- Privilege and Stacks
  105
- Pre-Emption
  107
- Figure 5-1 Stack Contents after Pre-Emption
  107
- Table 5-4 Exception Entry Steps
  108
- Figure 5-2 Exception Entry Timing
  109
- Tail-Chaining
  110
- Figure 5-3 Tail-Chaining Timing
  110
- Late-Arriving
  111
- Figure 5-4 Late-Arriving Exception Timing
  111
- Exit
  113
- Table 5-5 Exception Exit Steps
  113
- Figure 5-5 Exception Exit Timing
  114
- Table 5-6 Exception Return Behavior
  115
- Resets
  116
- Table 5-7 Reset Actions
  116
- Table 5-8 Reset Boot-Up Behavior
  117
- Exception Control Transfer
  120
- Table 5-9 Transferring to Exception Processing
  120
- Setting up Multiple Stacks
  121
- Abort Model
  123
- Table 5-10 Faults
  124
- Table 5-11 Debug Faults
  126
- Table 5-12 Fault Status and Fault Address Registers
  127
- Activation Levels
  128
- Table 5-13 Privilege and Stack of Different Activation Levels
  128
- Table 5-14 Exception Transitions
  128
- Table 5-15 Exception Subtype Transitions
  129
- Flowcharts
  130
- Figure 5-6 Interrupt Handling Flowchart
  130
- Figure 5-7 Pre-Emption Flowchart
  131
- Figure 5-8 Return from Interrupt Flowchart
  132
Chapter 6 Clocking and Resets

133
- Clocking
  134
- Table 6-1 Cortex-M3 Processor Clocks
  134
- Table 6-2 Cortex-M3 Macrocell Clocks
  134
- Resets
  136
- Table 6-3 Reset Inputs
  136
- Cortex-M3 Reset Modes
  137
- Table 6-4 Reset Modes
  137
- Figure 6-1 Reset Signals
  138
- Figure 6-2 Power-On Reset
  138
- Figure 6-3 Internal Reset Synchronization
  139
Chapter 7 Power Management

141
Chapter 8 Nested Vectored Interrupt Controller

151
Chapter 9 Memory Protection Unit

196
Chapter 10 Core Debug

216
Chapter 11 System Debug

230
Chapter 12 Bus Interface

274
- About Bus Interfaces
  274
- AMBA 3 Compliance
  275
- Icode Bus Interface
  276
- Table 12-1 Instruction Fetches
  276
- Dcode Bus Interface
  278
- System Interface
  279
- Unifying the Code Buses
  281
- Figure 12-1 Icode/Dcode Multiplexer
  281
- External Private Peripheral Interface
  282
- Access Alignment
  283
- Table 12-2 Bus Mapper Unaligned Accesses
  283
- Unaligned Accesses that Cross Regions
  284
- 12.10 Bit-Band Accesses
  285
- 12.11 Write Buffer
  286
- 12.12 Memory Attributes
  287
- Table 12-3 Memory Attributes
  287
- 12.13 AHB Timing Characteristics
  288
- Table 12-4 Interface Timing Characteristics
  288
Chapter 13 Debug Port

289
- About the DP
  290
Chapter 14 Embedded Trace Macrocell

292
- About the ETM
  292
- Figure 14-1 ETM Block Diagram
  293
- Table 14-1 ETM Core Interface Inputs and Outputs
  294
- Table 14-2 Miscellaneous Configuration Inputs
  294
- Table 14-3 Trace Port Signals
  295
- Table 14-4 Other Signals
  295
- Table 14-5 Clocks and Resets
  296
- Table 14-6 APB Interface Signals
  296
- Data Tracing
  297
- ETM Resources
  298
- Table 14-7 Cortex-M3 Resources
  298
- Trace Output
  301
- ETM Architecture
  302
- Figure 14-2 Return from Exception Packet Encoding
  302
- Table 14-8 Exception Tracing Mapping
  303
- Figure 14-3 Exception Encoding for Branch Packet
  304
- ETM Programmer's Model
  306
- Table 14-9 ETM Registers
  306
- Table 14-10 Boolean Function Encoding for Events
  312
- Table 14-11 Resource Identification Encoding
  313
- Table 14-12 Input Connections
  313
- Table 14-13 Trigger Output Connections
  313
Chapter 15 Embedded Trace Macrocell Interface

315
Chapter 16 AHB Trace Macrocell Interface

329
Chapter 17 Trace Port Interface Unit

334
Chapter 18 Instruction Timing

355
- About Instruction Timing
  356
- Processor Instruction Timings
  357
- Table 18-1 Instruction Timings
  357
- Load-Store Timings
  361
Chapter 19 AC Characteristics

363
Appendix A Signal Descriptions

374
- Clocks
  374
- A.1 Clocks
  374
- Table A-1 Clock Signals
  374
- Resets
  375
- A.2 Resets
  375
- Table A-2 Reset Signals
  375
- Miscellaneous
  376
- A.3 Miscellaneous
  376
- Table A-3 Miscellaneous Signals
  376
- Interrupt Interface
  378
- A.4 Interrupt Interface
  378
- Table A-4 Interrupt Interface Signals
  378
- Low Power Interface
  379
- Table A-5 Low Power Interface Signals
  379
- Icode Interface
  380
- Table A-6 Icode Interface
  380
- Dcode Interface
  381
- Table A-7 Dcode Interface
  381
- System Bus Interface
  382
- Table A-8 System Bus Interface
  382
- Private Peripheral Bus Interface
  383
- Table A-9 Private Peripheral Bus Interface
  383
- ITM Interface
  384
- Table A-10 ITM Interface
  384
- AHB-AP Interface
  385
- Table A-11 AHB-AP Interface
  385
- ETM Interface
  386
- Table A-12 ETM Interface
  386
- AHB Trace Macrocell Interface
  388
- Table A-13 HTM Interface
  388
- Test Interface
  389
- Table A-14 Test Interface
  389
- WIC Interface
  390
- A.15 WIC Interface
  390
- Table A-15 WIC Interface Signals
  390
Appendix B Revisions

391
- Table B-1 Differences between Issue E and Issue F
  391
- Table B-2 Differences between Issue F and Issue G
  395

ARM Cortex-M3 DesignStart Technical Reference Manual (400 pages)

Brand: ARM | Category: Computer Hardware | Size: 2 MB

ARM Cortex-M3 DesignStart User Manual (59 pages)

Brand: ARM | Category: Motherboard | Size: 0 MB

Document History
2
Table of Contents
4
Preface

6
- About this Book
  7
- Feedback
  10
Chapter 1 Introduction

11
Chapter 2 Using the Prebuilt FPGA Image

19
Chapter 3 FPGA Platform Overview

25
- System Overview
  25
- Memory Map
  26
- Block RAM Instances
  27
- External Zero Bus Turnaround SSRAM
  28
- External PSRAM
  29
- Arduino Adapter Board
  30
- Embedded Trace Macrocell Interface
  31
- CMSDK APB Subsystem
  32
- Ahb Gpio
  33
- Serial Peripheral Interface
  34
- Color LCD Parallel Interface
  35
- Ethernet
  36
- Vga
  37
- Audio I 2 S
  38
- Audio Configuration
  40
- FPGA System Control and I/O
  41
Chapter 4 Clocks

43
- Source Clocks
  43
- Derived Clocks
  44
Chapter 5 Serial Communication Controller

46
- SCC Interface Overview
  46
- SCC Memory Map
  47
- Build Flow
  50
- Build Requirements
  52
Chapter 6 FPGA Build

53
Chapter 7 Integrating with Mbed

53
Chapter 8 Performance and Utilization

58
Appendix A Revisions

58
- Revisions - Cortex -M3 Designstart Eval
  59

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ARM Cortex-M3 DesignStart Technical Reference Manual (410 pages)

Table of Contents

Preface

Chapter 1 Introduction

Chapter 2 Programmer's Model

Chapter 3 System Control

Chapter 4 Memory Map

Chapter 5 Exceptions

Chapter 6 Clocking and Resets

Chapter 7 Power Management

Chapter 8 Nested Vectored Interrupt Controller

Chapter 9 Memory Protection Unit

Chapter 10 Core Debug

Chapter 11 System Debug

Chapter 12 Bus Interface

Chapter 13 Debug Port

Chapter 14 Embedded Trace Macrocell

Chapter 15 Embedded Trace Macrocell Interface

Chapter 16 AHB Trace Macrocell Interface

Chapter 17 Trace Port Interface Unit

Chapter 18 Instruction Timing

Chapter 19 AC Characteristics

Appendix A Signal Descriptions

Appendix B Revisions

ARM Cortex-M3 DesignStart Technical Reference Manual (400 pages)

Table of Contents

Preface

Chapter 1 Introduction

Chapter 2 Programmer's Model

Chapter 3 System Control

Chapter 4 Memory Map

Chapter 5 Exceptions

Chapter 6 Clocking and Resets

Chapter 7 Power Management

Chapter 8 Nested Vectored Interrupt Controller

Chapter 9 Memory Protection Unit

Chapter 10 Core Debug

Chapter 11 System Debug

Chapter 12 Debug Port

Chapter 13 Trace Port Interface Unit

Chapter 14 Bus Interface

Chapter 15 Embedded Trace Macrocell

Chapter 16 Embedded Trace Macrocell Interface

Chapter 17 Instruction Timing

ARM Cortex-M3 DesignStart User Manual (59 pages)

Table of Contents

Preface

Chapter 1 Introduction

Chapter 2 Using the Prebuilt FPGA Image

Chapter 3 FPGA Platform Overview

Chapter 4 Clocks

Chapter 5 Serial Communication Controller

Chapter 6 FPGA Build

Chapter 7 Integrating with Mbed

Chapter 8 Performance and Utilization

Appendix A Revisions

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