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ARM DDI 0301H
ID012310
l.
IRQn, lowest priority IRQ
The processor core prioritization handles most of the priority structure, but the VIC
handles the priorities within each group of interrupts.
Note
This list reflects the priorities that the handlers are subject to, and differs from the
priorities that the exception entry sequences are subject to. The difference occurs because
simultaneous Data Abort and FIQ exceptions result in the sequence:
a.
Data Abort entry sequence executed, updating R14_abt, SPSR_abt, PC, and CPSR.
b.
FIQ entry sequence executed, updating R14_fiq, SPSR_fiq, PC, and CPSR.
c.
FIQ handler executes to completion and returns.
d.
Data Abort handler executes to completion and returns.
For more information see the ARM Architecture Reference Manual.
4.
Stack and register usage is:
•
The FIQ1 interrupt handler has exclusive use of R8_fiq to R12_fiq. In ARMv5,
R13_fiq points to a memory area, that is mainly for use by the FIQ1 handler.
However, a few words are used during entry for other FIQ handlers. In ARMv6, the
FIQ1 interrupt handler has exclusive use of R13_fiq.
•
The Undefined instruction, Prefetch Abort, Data Abort, and non-FIQ1 FIQ handlers
use the stack pointed to by R13_abt. This stack is locked down in memory, and
therefore of known, limited depth.
•
All IRQ and SVC handlers use the stack pointed to by R13_svc. This stack does not
have to be locked down in memory.
•
The stack pointed to by R13_usr is used by the current process. This process can be
privileged or unprivileged, and uses System or User mode accordingly.
5.
Timings are roughly consistent with ARM10 timings, with the pipeline reload penalty
being three cycles. It is assumed that pipeline reloads are combined to execute as quickly
as reasonably possible, and in particular that:
•
If an interrupt is detected during an instruction that has set a new value for the PC,
after that value has been determined and written to the PC but before the resulting
pipeline refill is completed, the pipeline refill is abandoned and the interrupt entry
sequence started as soon as possible.
•
Similarly, if an FIQ is detected during an exception entry sequence that does not
disable FIQs, after the updates to R14, the SPSR, the CPSR, and the PC but before
the pipeline refill has completed, the pipeline refill is abandoned and the FIQ entry
sequence started as soon as possible.
FIQs in the example system in ARMv5
In ARMv5, all FIQ interrupts come through the same vector, at address
0xFFFF001C
. To implement the above system, the code at this vector must get the address of the
correct handler from the VIC, branch to it, and transfer to using R13_abt and the Abort mode
stack if it is not the FIQ1 handler. The following code does, assuming that R8_fiq holds the
address of the VIC:
FIQhandler
LDR
PC, [R8,#HandlerAddress]
...
FIQ1handler
... Include code to process the interrupt ...
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0x0000001C
or
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