ARM ARM1176JZF-S Technical Reference Manual page 61

Operation
Status register
handling
Load
Load multiple
Soft preload
Store
ARM DDI 0301H
ID012310
Move SPSR to register
Move CPSR to register
Move register to SPSR
Move register to CPSR
Move immediate to SPSR flags
Move immediate to CPSR flags
Word
Word with User mode privilege
PC as destination, branch and
exchange
Byte
Byte with User mode privilege
Byte signed
Halfword
Halfword signed
Doubleword
Return from exception
Stack operations
Increment before
Increment after
Decrement before
Decrement after
Stack operations and restore CPSR
User registers
Memory system hint
In Non-secure this instruction
behaves like a
NOP
Word
Word with User mode privilege
Byte
Byte with User mode privilege
Halfword
Doubleword
Store return state
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Table 1-7 ARM instruction set summary (continued)
Assembler
MRS{cond} <Rd>, SPSR
MRS{cond} <Rd>, CPSR
MSR{cond} SPSR_{field}, <Rm>
MSR{cond} CPSR_{field}, <Rm>
MSR{cond} SPSR_{field}, #<immed_8r>
MSR{cond} CPSR_{field}, #<immed_8r>
LDR{cond} <Rd>, <a_mode2>
LDR{cond}T <Rd>, <a_mode2P>
LDR{cond} R15, <a_mode2P>
LDR{cond}B <Rd>, <a_mode2>
LDR{cond}BT <Rd>, <a_mode2P>
LDR{cond}SB <Rd>, <a_mode3>
LDR{cond}H <Rd>, <a_mode3>
LDR{cond}SH <Rd>, <a_mode3>
LDR{cond}D <Rd>, <a_mode3>
RFE<a_mode4> <Rn>{!}
LDM{cond}<a_mode4L> <Rn>{!}, <reglist>
LDM{cond}IB <Rn>{!}, <reglist>{^}
LDM{cond}IA <Rn>{!}, <reglist>{^}
LDM{cond}DB <Rn>{!}, <reglist>{^}
LDM{cond}DA <Rn>{!}, <reglist>{^}
LDM{cond}<a_mode4> <Rn>{!}, <reglist+pc>^
LDM{cond}<a_mode4> <Rn>{!}, <reglist>^
PLD <a_mode2>
STR{cond} <Rd>, <a_mode2>
STR{cond}T <Rd>, <a_mode2P>
STR{cond}B <Rd>, <a_mode2>
STR{cond}BT <Rd>, <a_mode2P>
STR{cond}H <Rd>, <a_mode3>
STR{cond}D <Rd>, <a_mode3>
SRS<a_mode4> <mode>{!}
Introduction
1-35