Table 21-3 Double-Precision Source Register Locking - ARM ARM1176JZF-S Technical Reference Manual

21.6.4 Double-precision source register locking
21.6.5 Double-precision source register clearing
ARM DDI 0301H
ID012310
In full-compliance mode, the source scoreboard locks all source registers in the Issue stage of
the instruction. In RunFast mode, the source scoreboard locks the source registers for only
iterations 3 and 4. Table 21-3 summarizes source register locking in double-precision
operations.
LEN
b000
b001
b010
b011
For the following double-precision, short vector instruction, the LEN field contains b011,
selecting a vector length of four iterations:
FADDD D4, D8, D12
The FADDD instruction performs the following operations:
FADDD D4, D8, D12
FADDD D5, D9, D13
FADDD D6, D10, D14
FADDD D7, D11, D15
In full-compliance mode, the source scoreboard locks D8-D11 and D12-D15 in the Issue stage
of the instruction.
In RunFast mode, the source scoreboard locks only the third iteration source registers, D10 and
D14, and the fourth iteration source registers, D11 and D15.
The number of Execute 1 cycles required to clear the source registers of a double-precision
instruction depends on the throughput of the instruction, as the following sections show:
• Instructions with one-cycle throughput on page 21-11
• Instructions with two-cycle throughput on page 21-11.
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Table 21-3 Double-precision source register locking

Source registers locked in Issue stage
Vector length Full-compliance mode
1 Iteration 1 registers
2 Iteration 1-2 registers
3 Iteration 1-3 registers
4 Iteration 1-4 registers
VFP Instruction Execution
RunFast mode
-
-
Iteration 3 registers
Iteration 3-4 registers
21-10