Figure 4-9 Store Halfword, Big-Endian; Figure 4-10 Load Word, Little-Endian - ARM ARM1176JZF-S Technical Reference Manual

4.3.10 Load word, little-endian
4.3.11 Load word, big-endian
ARM DDI 0301H
ID012310
If strict alignment fault checking is enabled and Address bit 0 is not zero, then a Data Abort is
generated and the MMU returns a Misaligned fault in the Fault Status Register.
The addressed byte-quad is loaded from memory into the 32-bit general-purpose register so that
the least-significant addressed byte in memory appears in bits [7:0] of the ARM register, as
Figure 4-10 shows.
If strict alignment fault checking is enabled and Address bits [1:0] are not zero, then a Data
Abort is generated and the MMU returns a Misaligned fault in the Fault Status Register.
The addressed byte-quad is loaded from memory into the 32-bit general-purpose register so that
the most significant addressed byte in memory appears in bits [31:24] of the ARM register, as
Figure 4-11 on page 4-11 shows.
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Unaligned and Mixed-endian Data Access Support
Register
31 23 15 7
x x B0 B1
Memory
7 0
Address
A[31:0]
b0 lsbyte
+1 b1
+2 b2
+3 b3 msbyte
Memory
7
Address
A[31:0]
0
+1

Figure 4-9 Store halfword, big-endian

Register
31 23 15
b3 b2

Figure 4-10 Load word, little-endian

0
B0 msbyte
B1 lsbyte
7 0
b1 b0
4-10