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14.7.9
Example sequences
ARM DDI 0301H
ID012310
Sticky Undefined flag
This section includes some example sequences to illustrate how to transfer data between the
DBGTAP debugger and the core when it is in Debug state. The examples are related to accessing
the processor memory.
Target to host transfer
The DBGTAP debugger can use the following sequence for reading data from the processor
memory system. The sequence assumes that the ARM register R0 contains a pointer to the
address of memory where the read has to start:
1.
Scan_N into the IR.
2.
1 into the SCREG.
3.
INTEST into the IR.
4.
Scan out the contents of the DSCR. This clears the sticky precise Data Abort, sticky
imprecise Data Abort flags, and sticky Undefined flags.
5.
Scan_N into the IR.
6.
4 into the SCREG.
7.
EXTEST into the IR.
8.
Scan in the
LDC p14,c5,[R0],#4
9.
Scan_N into the IR.
10.
5 into the SCREG.
11.
INTEST into the IR.
12.
Go through Run-Test/Idle state. The instruction loaded into the ITR is issued to the
processor pipeline.
13.
Scan out 34 bits of data. If the Ready flag is clear, repeat this step again.
14.
The instruction has completed execution. Store the least significant 32 bits.
15.
Go to step 13 again for reading out more data.
16.
Scan_N into the IR.
17.
1 into the SCREG.
18.
INTEST into the IR.
19.
Scan out the contents of the DSCR. This clears the sticky precise Data Abort and sticky
imprecise Data Abort and sticky Undefined flags. If the sticky precise Data Abort is set,
this means that during the sequence one of the instructions caused a precise Data Abort.
Not all the instructions that follow are executed. Register R0 points to the next word to be
read, and after the cause for the abort has been fixed the sequence resumes at step 5.
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DSCR[8]. When set, this flag indicates to the DBGTAP debugger
that an Undefined exception occurred while executing an instruction
in Debug state. This flag does not disable the Debug state instruction
execution.
instruction into the ITR.
Debug Test Access Port
14-26
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