ARM ARM946E-S Technical Reference Manual

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ARM946E-S

Technical Reference Manual

ARM DDI 0155A

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Page 1 ARM946E-S Technical Reference Manual ARM DDI 0155A...
Page 2 This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 3: Table Of Contents
About the ARM94E-S programmer’s model..........2-2 About the ARM9E-S programmer’s model............ 2-3 CP15 register map summary ................ 2-4 Chapter 3 Caches Cache architecture..................3-2 ICache......................3-6 DCache ......................3-8 Cache lockdown..................3-12 ARM DDI 0155A-04 Copyright © ARM Limited 2000. All rights reserved. Limited Confidential...
Page 4 Enabling the ETM interface ................9-4 Chapter 10 Test Support 10.1 About the ARM946E-S test methodology........... 10-2 10.2 Scan insertion and ATPG ................10-3 10.3 BIST of memory arrays................10-5 Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A-04 Limited Confidential...
Page 5 Clock interface signals ..................B-3 AHB signals ....................B-4 Coprocessor interface signals...............B-6 Debug signals ....................B-8 JTAG signals....................B-10 Miscellaneous signals .................B-11 ETM interface signals .................B-12 INTEST wrapper signals ................B-14 Index ARM DDI 0155A-04 Copyright © ARM Limited 2000. All rights reserved. Limited Confidential...
Page 7 Table 2-18 Area size encoding................2-21 Table 2-19 Cache operations ................2-22 Table 2-20 Index fields for supported cache sizes ..........2-23 Table 2-21 Lockdown register format..............2-25 Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A Limited Confidential...
Page 8 Table B-5 JTAG signals ..................B-10 Table B-6 Miscellaneous signals ................ B-11 Table B-7 ETM interface signals ................ B-12 Table B-8 INTEST wrapper signals ..............B-14 Copyright © ARM Limited 2000. All rights reserved. viii ARM DDI 0155A Limited Confidential...
Page 9 Data burst followed by instruction fetch ..........6-6 Figure 6-5 Crossing a 1KB boundary ..............6-7 Figure 6-6 AHB clock relationships ..............6-10 Figure 6-7 ARM946E-S CLK to AHB HCLK sampling.......... 6-11 Figure 7-1 Coprocessor clocking................7-2 Figure 7-2 LDC/STC cycle timing ................7-4 Figure 7-3 MCR/MRC transfer timing with busy-wait ..........
Page 10 DBGSDOUT to DBGTDO timing ............A-6 Figure A-8 Exception and configuration timing ............A-7 Figure A-9 INTEST wrapper timing ............... A-7 Figure A-10 ETM interface timing ................A-8 Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A Limited Confidential...
Page 11: Preface
Preface This preface introduces the ARM946E-S and its reference documentation. It contains the following sections: • About this document on page xii • Further reading on page xv • Feedback on page xvi. Copyright © ARM Limited 2000. All rights reserved.
Page 12: About This Document
This document is a reference manual for the ARM946E-S. Intended audience This document has been written for hardware and software engineers who want to design or develop products based upon the ARM946E-S processor. It assumes no prior knowledge of ARM products. Using this manual...
Page 13 Chapter 8 Debug Support This chapter describes the debug support for the ARM946E-S and the EmbeddedICE-RT logic. Chapter 9 ETM Interface This chapter describes the ETM interface, including details of how to enable the interface. Chapter 10 Test Support This chapter describes the test methodology used for the ARM946E-S synthesized logic and tightly-coupled SRAM.
Page 14 Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 15: Further Reading
Further reading This section lists publications by ARM Limited, and by third parties. If you would like further information on ARM products, or if you have questions not answered by this document, please contact info@arm.com or visit our web site at http://www.arm.com.
Page 16: Feedback
Feedback ARM Limited welcomes feedback both on the ARM946E-S, and on the documentation. Feedback on the ARM946E-S If you have any comments or suggestions about this product, please contact your supplier giving: • the product name • a concise explanation of your comments...
Page 17: Chapter 1 Introduction
Chapter 1 Introduction This chapter introduces the ARM946E-S processor. It contains the following sections: • About the ARM946E-S on page 1-2 • Microprocessor block diagram on page 1-3. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 18: About The Arm946E-S
Introduction About the ARM946E-S The ARM946E-S is a synthesizable macrocell combining an ARM processor. It is a member of the ARM9 Thumb family of high-performance, 32-bit system-on-chip processor solutions. The ARM946E-S has tightly-coupled SRAM memory, and instruction and data caches and is targeted at a wide range of embedded applications where high-performance, low system cost, small die size and low power are all important.
Page 19: Microprocessor Block Diagram
Introduction Microprocessor block diagram The ARM946E-S block diagram is shown in Figure 1-1. Data Instruction System control External SRAM SRAM coprocessor Bus interface unit coprocessor (CP15) and write buffer interface Addr Addr WDATA ARM9E-S INSTR RDATA interface Memory System Instruction...
Page 20: Chapter 2 Programmer's Model
Chapter 3 Caches Data cache Chapter 3 Caches Instruction cache control Chapter 2 Programmer’s Model and Chapter 3 Caches Data cache control Chapter 2 Programmer’s Model and Chapter 3 Caches Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 21 Chapter 2 Programmer’s Model This chapter describes the programmer’s model for the ARM946E-S. It contains the following sections: • About the ARM94E-S programmer’s model on page 2-2 • About the ARM9E-S programmer’s model on page 2-3 • CP15 register map summary on page 2-4.
Page 22: About The Arm94E-S Programmer's Model
CP14 within the ARM9E-S core allows software access to the debug communications channel • CP15 allows configuration of the caches, tightly-coupled SRAM, protection unit, write buffer, and other ARM946E-S system options such as big or little-endian operation. The registers defined in CP14 are accessible with instructions, and are described in The debug communications channel on page 8-29.
Page 23: About The Arm9E-S Programmer's Model
About the ARM9E-S programmer’s model The ARM9E-S processor core implements the ARMv5TExP architecture, which includes the 32-bit ARM instruction set and the 16-bit Thumb instruction set. For a description of both instruction sets, see the ARM Architecture Reference Manual. Contact ARM for complete descriptions of both instruction sets.
Page 24: Cp15 Register Map Summary
Programmer’s Model CP15 register map summary The ARM946E-S incorporates CP15 for system control. CP15 allows configuration of the caches, tightly-coupled SRAM, and protection unit. It also allows configuration of ARM946E-S system options including big or little-endian operation. The register map for CP15 is shown in Table 2-1.
Page 25: Table 2-2 Cp15 Abbreviations
All CP15 register bits that are defined and contain state, are set to zero by HRESETn except V-Bit in register 1, that takes the value of macrocell input VINITHI when HRESETn is asserted. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 26: Figure 2-1 Cp15 Mrc And Mcr Bit Pattern
CP15 register 0 with the field set to any value other opcode_2 than 1 or 2. For example: MRC p15, 0, rd, c0, c0, {0,3-7}; returns ID register Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 27: Table 2-3 Register 0, Id Code
This is a read-only register that contains information about the size and architecture of the instruction cache (ICache) and data cache (DCache), allowing operating systems to establish how to perform operations such as cache cleaning and lockdown. Future ARM cached processors will contain this register, allowing RTOS vendors to produce future-proof versions of their operating systems.
Page 28: Table 2-5 Cache Size Encoding
Table 2-5 lists the meaning of values used for cache size encoding. Table 2-5 Cache size encoding Bits [21:18] and Cache size bits[9:6] b0000 b0011 b0100 b0101 16KB b0110 32KB b0111 64KB b1000 128KB b1001 256KB b1010 512KB b1011 Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 29: Table 2-6 Cache Associativity Encoding
The tightly-coupled memory size register is accessed by reading CP15 register 0 with field set to 2. For example: opcode_2 MRC p15, 0, rd, c0, c0, 2; returns tightly-coupled memory size register Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 30: Table 2-7 Tightly-Coupled Memory Size Register
RAM memory sizes. Table 2-8 Memory size field Bits [21:8] and bits Tightly-coupled [9:6] RAM size b0000 b0011 b0100 b0101 16KB b0110 32KB b0111 64KB b1000 128KB Copyright © ARM Limited 2000. All rights reserved. 2-10 ARM DDI 0155A...
Page 31: Table 2-9 Register 1, Control Register
2.3.5 Register 1, Control register This register contains the control bits of the ARM946E-S. All reserved bits must either be written with zero or one, as indicated, or written using read-modify-write. The reserved bits have an unpredictable value when read. To read and write this register: MRC p15, 0, rd, c1, c0, 0;...
Page 32 You can use the instruction RAM load mode for initializing the instruction RAM. The instruction RAM load mode allows you to load data into ARM registers from either data cache or main memory, and then write to the same address but within the tightly-coupled instruction RAM.
Page 33 You can use the data RAM load mode for initializing the data RAM. The data RAM load mode allows you to load data into ARM registers from either data cache or main memory, and then write to the same address but within the tightly-coupled data RAM.
Page 34 HIGH. This can be done with a single write to register 1. At reset this bit is cleared. Bit 7, Endian Selects the endian configuration of the ARM946E-S. When this bit is HIGH, big-endian configuration is selected. When LOW, little-endian configuration is selected. At reset this bit is cleared.
Page 35: Table 2-10 Programming Instruction/Data Cachable Bits
Register 3, Write buffer control register This register contains the write buffer control (bufferable) attribute for the eight areas of memory. Note This register only applies to data accesses. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 2-15...
Page 36: Table 2-11 Programming Data Bufferable Bits
MCR p15, 0, rd, c5, c0, 3; write instruction access permission bits The format for the access permission bits in instruction and data areas is the same, and is given in Table 2-12 on page 2-17. Copyright © ARM Limited 2000. All rights reserved. 2-16 ARM DDI 0155A...
Page 37: Table 2-12 Programming Instruction And Data Access Permission Bits (Extended)
No access No access 0001 Read/write access No access 0010 Read/write access Read-only 0011 Read/write access Read/write access 0100 0101 Read-only No access 0110 Read-only Read-only 0111 1xxx Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 2-17...
Page 38: Table 2-14 Instruction And Data Access Permission Bits (Standard)
Programmer’s Model The following instructions are supported for backwards compatibility with existing ARM processors with memory protection, and access the standard registers: MRC p15, 0, rd, c5, c0, 0; read data access permission bits MRC p15, 0, rd, c5, c0, 1; read instruction access permission bits MCR p15, 0, rd, c5, c0, 0;...
Page 39: Table 2-15 Access Permission Encoding (Standard)
0. All other bits are undefined. You must program at least one memory region before you enable the protection unit. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 2-19...
Page 40: Table 2-16 Accessing Protection Region/Base Size Registers
You must align the region base to an area size boundary, where the area size is defined in its respective protection region register. The behavior is unpredictable if this is not done. Copyright © ARM Limited 2000. All rights reserved. 2-20 ARM DDI 0155A...
Page 41: Table 2-18 Area Size Encoding
32KB 01111 64KB 10000 128KB 10001 256KB 10010 512KB 10011 10100 10101 10110 10111 16MB 11000 32MB 11001 64MB 11010 128MB 11011 256MB 11100 512MB 11101 11110 11111 Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 2-21...
Page 42: Table 2-19 Cache Operations
• clean and flush the DCache. The ARM946E-S uses a subset of the ARM architecture v4 functions (defined in the ARM Architecture Reference Manual). The available operations are summarized in Table 2-19. Table 2-19 Cache operations...
Page 43: Table 2-20 Index Fields For Supported Cache Sizes
Figure 2-2 Index and segment format The size of the index varies depending on the implemented cache size. Table 2-20 shows how the index size changes for the cache sizes supported by the ARM946E-S. Table 2-20 Index fields for supported cache sizes...
Page 44: Figure 2-3 Icache Address Format
Wait for interrupt This operation allows the ARM946E-S to enter a low-power standby mode. When you invoke the operation, the CLKEN signal to the processor core is negated and the cache and tightly-coupled memories are placed in a low-power state until either an interrupt or a debug request occurs.
Page 45: Table 2-21 Lockdown Register Format
The format of the register, rd, transferred during this operation is shown in Table 2-21. Table 2-21 Lockdown register format Register bit Function Load bit 30:2 UNP/SBZ Cache segment Lockdown is described in Cache lockdown on page 3-12. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 2-25...
Page 46: Table 2-22 Protection Region/Base Size Register Format
For a given number of aliases for the physical memory size, the following function can be used: Area size = Physical size + N where 2 is the required number of aliases. Copyright © ARM Limited 2000. All rights reserved. 2-26 ARM DDI 0155A...
Page 47: Table 2-23 Tightly-Coupled Memory Area Size Encoding
32KB b00111 64KB b01000 128KB b01001 256KB b01010 512KB b01011 b01100 b01101 b01110 b01111 16MB b10000 32MB b10001 64MB b10010 128MB b10011 256MB b10100 512MB b10101 b10110 b10111 Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 2-27...
Page 48 The contents of this register are replicated on the ETMPROCID pins of the ARM946E-S. The following ARM instructions are used for accessing the Process ID register: MRC p15, 0, rd, c13, c1, 1; read process ID register MCR p15, 0, rd, c13, c1, 1; write process ID register Copyright ©...
Page 49: Table 2-24 Register 15, Bist Instructions
2.3.14 Register 15, RAM and TAG BIST test registers Register 15 gives you access to the test features included within the ARM946E-S. The register map for CP15 register 15 BIST-related instructions is shown in Table 2-24. Table 2-24 Register 15, BIST instructions...
Page 50: Table 2-26 Test State Register Bit Assignments
MCR p15, 2, Rd, c15, c0, 7 register Note ARM recommends that you do not write application code that relies on the presence of the BIST address and general registers. ARM does not guarantee to support these registers in future versions of the ARM946E-S.
Page 51: Table 2-27 Additional Operations
2.3.16 Register 15, Cache debug index register Register 15 gives you access to the test features included within the ARM946E-S. Additional instructions and operations are required to support debug operations within the cache. Instructions for the additional operations are listed in Table 2-27.
Page 52: Figure 2-5 Index/Segment Format
The data format for the TAG read/write operations is shown in Figure 2-6. N+1 N 5 4 3 2 1 0 Dirty TAG address Index bits Valid Figure 2-6 Data format TAG read/write operations Copyright © ARM Limited 2000. All rights reserved. 2-32 ARM DDI 0155A...
Page 53: Table 2-28 Index Fields For Supported Cache Sizes
Table 2-28 Index fields for supported cache sizes Cache size Index Addr[31:10] Addr[9:5] Addr[31:11] Addr[10:5] 16KB Addr[31:12] Addr[11:5] 32KB Addr[31:13] Addr[12:5] 64KB Addr[31:14] Addr[13:5] 128KB Addr[31:15] Addr[14:5] 256KB Addr[31:16] Addr[15:5] 512KB Addr[31:17] Addr[16:5] Addr[31:18] Addr[17:5] Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 2-33...
Page 55 Chapter 3 Caches To reduce the effective memory access time, the ARM946E-S uses a cache controller, an Instruction Cache (ICache), and a Data Cache (DCache). This chapter describes the features and behavior of each of these blocks. It contains the following sections: •...
Page 56: Chapter 3 Caches
Caches Cache architecture The ARM946E-S incorporates ICache and DCache. You can tailor the size of these to suit individual applications. A range of different cache sizes is supported: • • • • 16KB • 32KB • 64KB • 128KB •...
Page 58: Table 3-1 Tag And Index Fields For Supported Cache Sizes
Table 3-1 TAG and index fields for supported cache sizes Cache size Index Addr[9:5] Addr[31:10] Addr[10:5] Addr[31:11] 16KB Addr[11:5] Addr[31:12] 32KB Addr[12:5] Addr[31:13] 64KB Addr[13:5] Addr[31:14] 128KB Addr[14:5] Addr[31:15] Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 60: Icache
Caches ICache The ARM946E-S has a four-way set-associative ICache. You can choose the size of the ICache from any of the supported cache sizes. The ICache uses the physical address generated by the processor core. It uses a policy of allocate on read-miss, and is always reloaded one cache line (eight words) at a time, through the external interface.
Page 61 As shown in Table 2-19 on page 2-22, you can flush the entire ICache using an instruction. In this case, the contents of the ARM register transferred to CP15 must be zero. You can use the following code segment to do this: MOV r0, #0 ;...
Page 62: Dcache
Caches DCache The ARM946E-S has a four-way set-associative DCache. You can choose the size of the DCache from any of the supported cache sizes. The DCache uses the physical address generated by the processor core. It uses an allocate on read-miss policy, and is always reloaded one cache line (eight words) at a time, through the external interface.
Page 63: Table 3-2 Meaning Of Cd Bit Values
Load and store multiples are broken up on 4KB boundaries (the minimum protection region size), allowing a protection check to be performed in case the Load Multiple ) or Store Multiple ( ) crosses into a region with different protection properties. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 64: Figure 3-3 Register 7, Rd Format
The ARM946E-S does not support memory translation so you can always consider the data in the DCache as valid within the context of the ARM946E-S. However, if you use external memory translation, and the mappings are changed, the DCache is no longer consistent with external memory, and you must flush it.
Page 65: Table 3-3 Calculating Index Addresses
; If not branch back to inner_loop ADD r1, r1, #0x40000000 ; Increment segment counter CMP r1, #0x0 ; Complete all segments BNE outer_loop ; If not branch back to outer_loop Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 3-11...
Page 66: Cache Lockdown
You can carry out lockdown in the DCache using CP15 register 9. ICache lockdown uses both CP15 registers 7 and 9. As described in Cache architecture on page 3-2, the ARM946E-S ICache and DCache each comprise four segments. You can perform lockdown with a granularity of one segment.
Page 68 - Interrupts must be disabled - Subroutine must be called using the BL instruction - r1-r3 can be corrupted in line with ARM/Thumb Procedure Call Standards (ATPCS) - Returns final ICache lockdown index in r0 if successful...
Page 69 MCR p15, 0, r3, c9, c0, 1 ;Write lockdown register MOV pc, lr ;Return from subroutine error MVN r0, #0 ;Move 0xFFFFFFFF into r0 MOV pc, lr ;Return from subroutine Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 3-15...
Page 71 Chapter 4 Protection Unit This chapter describes the ARM946E-S protection unit. It contains the following sections: • About the protection unit on page 4-2 • Memory regions on page 4-3 • Overlapping regions on page 4-6. Copyright © ARM Limited 2000. All rights reserved.
Page 72: Chapter 4 Protection Unit
Enabling the protection unit Before the protection unit is enabled, you must program at least one valid protection region. If you do not do this the ARM946E-S can enter a state that is recoverable only by reset. Setting bit 0 of the CP15 register 1, the control register, enables the protection unit.
Page 73: Memory Regions
• read and write access permissions. The ARM architecture uses constants known as inline literals to perform address calculations. These constants are automatically generated by the assembler and compiler and are stored inline with the instruction code. To ensure correct operation, you must define an area of memory, from where code is to be executed, that allows both data and instruction accesses.
Page 74: Table 4-2 Region Size Encoding
11000 32MB 11001 64MB 11010 128MB 11011 256MB 11100 512MB 11101 11110 11111 Note Any value less than b01011 programmed in CP15 register 6 bits[5:1] results in unpredictable behavior. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 76: Overlapping Regions
4GB address space. If a programming error occurs therefore, it might be possible for the processor to issue an address that does not fall into any defined region. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 77 If the address issued by the processor falls outside any of the defined regions, the ARM946E-S protection unit is hard-wired to abort the access. You can override this behavior by programming region 0 to be a 4GB background region. In this way, if the address does not fall into any of the other seven regions, the access is controlled by the attributes you have specified for region 0.
Page 79: Chapter 5 Tightly-Coupled Sram
Chapter 5 Tightly-coupled SRAM This chapter describes the tightly-coupled SRAM in the ARM946E-S. It contains the following sections: • ARM946E-S SRAM requirements on page 5-2 • Using CP15 control register on page 5-3. For details of the ARM9E-S interface signals referenced in this chapter, see the ARM9E-S Technical Reference Manual.
Page 80: Arm946E-S Sram Requirements
Tightly-coupled SRAM ARM946E-S SRAM requirements The ARM946E-S tightly-coupled SRAM is built from blocks of ASIC library compiled SRAM. The instruction SRAM (I-SRAM) and data SRAM (D-SRAM) can each be of any size supported by the protection unit, from 0 bytes to 1MB, although to ease implementation the size must be an integer power of two.
Page 81: Using Cp15 Control Register
ARM9E-S instruction fetches and data accesses to the I-SRAM address space cause the I-SRAM to be accessed. Enabling the I-SRAM greatly increases the performance of the ARM946E-S because the majority of accesses to it can be performed with no stall cycles. Accessing the AHB however, can cause several stall cycles for each access.
Page 82 The procedure for initializing the I-SRAM using the load mode is as follows: Enable the I-SRAM and instruction load mode Load ARM registers from main memory, data cache or data RAM Store ARM registers into I-SRAM Increment address pointers and repeat load/store steps until the code image has been copied.
Page 83 The procedure for initializing the D-SRAM using the load mode is as follows: Enable the D-SRAM and data load mode Load ARM registers from main memory or data cache Store ARM registers into data RAM Increment address pointers and repeat load/store steps until the data image has been copied.
Page 84 The read accesses external memory or the data cache, and the write updates the data tightly-coupled memory. operations must not be performed to addresses in the instruction SWPB tightly-coupled SRAM space while it is in load mode. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 85 Chapter 6 Bus Interface Unit and Write Buffer This chapter describes the ARM946E-S Bus Interface Unit (BIU) and write buffer. It contains the following sections: • About the BIU and write buffer on page 6-2 • AHB bus master interface on page 6-3 •...
Page 86: Chapter 6 Bus Interface Unit And Write Buffer
See the AMBA Rev 2.0 AHB Specification for full details of this bus architecture. The ARM946E-S BIU implements a fully-compliant AHB bus master interface and incorporates a write buffer to increase system performance. The BIU is the link between the ARM9E-S core with the caches and tightly-coupled SRAM and the external AHB memory.
Page 87: Ahb Bus Master Interface
Bus Interface Unit and Write Buffer AHB bus master interface The ARM946E-S implements a fully compliant AHB bus master interface as defined in the AMBA Rev 2.0 Specification. See this document for a detailed description of the AHB protocol. 6.2.1...
Page 88: Table 6-1 Supported Burst Types
Incrementing bursts have an address increment of four (that is, word increment). 6.2.4 Linefetch transfers The ARM946E-S is optimized to run with both the ICache and DCache enabled. If a memory request (either instruction or data) to a cachable area misses in the cache the ARM946E-S performs a linefetch.
Page 89: Figure 6-2 Back To Back Linefetches
Figure 6-2 Back to back linefetches 6.2.6 Uncached transfers If a memory request is made to an uncachable region, or the ARM946E-S cache is not enabled, the memory requests are serviced by the AHB interface. Sequential instruction fetches are treated as nonsequential reads.
Page 90: Figure 6-3 Nonsequential Uncached Accesses
Linefetches and cache line write backs cannot cross a 1KB boundary because the start address is aligned to either a four or eight-word boundary, and the burst length is fixed. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 91: Figure 6-5 Crossing A 1Kb Boundary
6-5. The burst is restarted by inserting a nonsequential transfer as the boundary is crossed. HTRANS NSEQ NSEQ IDLE HADDR 0x3F0 0x3F4 0x3F8 0x3FC 0x400 0x404 0x404 Figure 6-5 Crossing a 1KB boundary Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 92: Noncached Thumb Instruction Fetches
AHB transfers are only performed for nonsequential addresses and for sequential addresses that cross a word boundary. The word returned from main memory is latched so that both halfwords are available for the processor core. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 93: Ahb Clocking
If the slave being accessed at the HCLK rate has a multi-cycle response, the HREADY input to the ARM946E-S is driven LOW until the data is ready to be returned. The BIU must therefore perform a logical AND on the HREADY response with HCLKEN to detect that the AHB transfer has completed.
Page 94: Figure 6-6 Ahb Clock Relationships
ARM946E-S. You can achieve this using a clock tree insertion tool, if the clock tree is inserted for the ARM946E-S and the embedded system at the same time (top level insertion).
Page 95: Figure 6-7 Arm946E-S Clk To Ahb Hclk Sampling
In Figure 6-7, the slave peripheral has an input setup and hold, and an output hold and valid time relative to HCLK. The ARM946E-S has an input setup and hold, and an output hold and valid time relative to CLK’, the clock at the bottom of the clock tree.
Page 96: The Write Buffer
Bus Interface Unit and Write Buffer The write buffer The ARM946E-S provides a write buffer to improve system performance. The write buffer has a 16-entry FIFO. Each entry can be either address or data. The type of entry is determined by the setting of an address/data flag. Each address entry is tagged with the size of transfer, as indicated by the ARM9E-S core (byte, halfword, or word).
Page 97 Instruction fetches and NCNB reads bypass the write buffer. If you write self-modifying code to a bufferable or cachable region, then it is essential that you drain the write buffer before fetching instructions from these addresses. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 6-13...
Page 99 Chapter 7 Coprocessor Interface This chapter describes the ARM946E-S pipelined coprocessor interface. It contains the following sections: • About the coprocessor interface on page 7-2 • LDC/STC on page 7-4 • MCR/MRC on page 7-8 • Interlocked MCR on page 7-10 •...
Page 100: Chapter 7 Coprocessor Interface
Technical Reference Manual. Coprocessors determine the instructions they must execute using a pipeline follower in the coprocessor. As each instruction arrives from memory it enters both the ARM pipeline and the coprocessor pipeline. To avoid a critical path for the instruction being registered by the coprocessor, the coprocessor pipeline operates one clock cycle behind the ARM9E-S core pipeline.
Page 101 There are three classes of coprocessor instructions: Load from memory to coprocessor, or store from coprocessor to LDC/STC memory. Register transfer between coprocessor and ARM processor core. MCR/MRC Coprocessor data operation. The following sections give examples of how a coprocessor must execute these instruction classes: •...
Page 102: Ldc/Stc
LDC/STC instructions are used respectively to transfer data to and from external coprocessor registers and memory. For the ARM946E-S, the memory can be either internal memory (cache or tightly-coupled memory) or AHB depending on the address range of the access and the protection unit settings.
Page 103 If a new instruction is entering the Execute stage in the next cycle, it examines CHSDE[1:0]. • If the currently executing coprocessor instruction requires another Execute cycle, it examines CHSEX[1:0]. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 104 . Also in this cycle, DnMREQ is driven LOW, indicating to the ARM946E-S memory system that a memory access is required at the data end of the device. The timing for the data on CPDOUT and CPDIN is shown in Figure 7-2 on page 7-4.
Page 105: Table 7-1 Handshake Encoding
Meaning ABSENT WAIT LAST Note If an external coprocessor is not attached in the ARM946E-S embedded system, the CHSDE[1:0] and CHSEX[1:0] handshake inputs must be tied off to indicate ABSENT. 7.2.3 Multiple external coprocessors If multiple external coprocessors are to be attached to the ARM946E-S interface, you can combine the handshaking signals by ANDing bit 1, and ORing bit 0.
Page 106: Mcr/Mrc
CHSDE[1:0] as required. In the next cycle nCPMREQ is driven LOW to denote that the instruction has now been issued to the Execute stage. If Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 107 In the case of an , CPDIN[31:0] is sampled at the end of the ARM9E-S core Memory stage and written to the destination register during the next cycle. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 108: Interlocked Mcr
Execute Memory Write Coprocessor (interlock) (WAIT) (LAST) pipeline MCR/ CPINSTR[31:0] nCPMREQ CPPASS CPLATECANCEL CHSDE[1:0] WAIT WAIT CHSEX[1:0] LAST Ignored CPDOUT[31:0] CPDIN[31:0] Figure 7-4 Interlocked MCR/MRC timing with busy-wait Copyright © ARM Limited 2000. All rights reserved. 7-10 ARM DDI 0155A...
Page 109: Cdp
CPASS. In the following cycle CPLATECANCEL is asserted. This causes the coprocessor to terminate execution of the instruction and for it to cause no state changes to the coprocessor. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 7-11...
Page 110: Privileged Instructions
The first two CHSDE[1:0] responses are ignored by the ARM9E-S because it is only the final CHSDE[1:0] response, as the instruction moves from Decode into Execute, that counts. This allows the coprocessor to change its response as nCPTRANS changes. Copyright © ARM Limited 2000. All rights reserved. 7-12 ARM DDI 0155A...
Page 111: Busy-Waiting And Interrupts
Execute Execute Execute Execute Coprocessor (WAIT) (WAIT) (WAIT) (WAIT) interrupted pipeline CPINSTR[31:0] CPInstr nCPMREQ CPPASS CPLATECANCEL CHSDE[1:0] WAIT CHSEX[1:0] WAIT WAIT WAIT Ignored Figure 7-7 Busy-waiting and interrupts Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 7-13...
Page 113 Chapter 8 Debug Support This chapter describes the ARM946E-S debug interface. It contains the following sections: • About the debug interface on page 8-2 • Debug systems on page 8-4 • The JTAG state machine on page 8-7 • Scan chains on page 8-12 •...
Page 114: About The Debug Interface
• an external debug request. This is known as debug state. In debug state, the core and ARM946E-S memory system are effectively stopped, and isolated from the rest of the system. This is known as halt mode operation and allows you to examine the internal state of the ARM9E-S core, ARM946E-S system, and external AHB state, while all other system activity continues as normal.
Page 115: Figure 8-1 Clock Synchronization
Debug Support 8.1.1 Debug clocks You must synchronize the system and test clocks externally to the ARM946E-S macrocell. The ARM Multi-ICE debug agent directly supports one or more cores within an ASIC design. To synchronize off-chip debug clocking with the ARM946E-S macrocell you must use a three-stage synchronizer.
Page 116: Debug Systems
Debug Support Debug systems The ARM946E-S forms one component of a debug system that interfaces from the high-level debugging performed by the user to the low-level interface supported by the ARM946E-S. Figure 8-2 shows a typical debug system. Debug Debug...
Page 117 8.2.2 The protocol converter An interface, such as a parallel port, connects the debug host to the ARM946E-S development system. The messages broadcast over this connection must be converted to the interface signals of the ARM946E-S. The protocol converter performs the conversion.
Page 118: Figure 8-3 Arm9E-S Block Diagram
15. This is used for debug access to the CP15 register bank, to allow you to configure the system state within the ARM946E-S while in debug state, for instance to enable or disable the SRAM before performing a debug load or store.
Page 119: The Jtag State Machine
Exit2-DR Exit2-IR tms=1 tms=1 Update-DR Update-IR tms=1 tms=0 tms=1 tms=0 Figure 8-4 Test access port (TAP) controller state transitions 1. From IEEE Std 1149.1-1990. Copyright 1999IEEE. All rights reserved. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 120 Instruction register The instruction register is four bits in length. There is no parity bit. The fixed value loaded into the instruction register during the CAPTURE-IR controller state is 0001. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 121: Table 8-1 Public Instructions
SCAN_N (0010) This instruction connects the scan path select register between TDI and TDO. During the CAPTURE-DR state, the fixed value 10000 is loaded into the register. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 122 ID register on the TDO pin, while data is shifted in on the TDI pin into the ID register. In the UPDATE-DR state, the ID register is unaffected. BYPASS (1111) The BYPASS instruction connects a 1-bit shift register (the bypass register) between TDI and TDO. Copyright © ARM Limited 2000. All rights reserved. 8-10 ARM DDI 0155A...
Page 123 TDI and TDO and the TAP controller behaves as if the BYPASS instruction is loaded. The processor resynchronizes back to the memory system when the RUN-TEST/IDLE state is entered. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 8-11...
Page 124: Scan Chains
Debug Support Scan chains ARM946E-S supports 32 scan chains. Three scan chains are used inside ARM946E-S. These allow testing, debugging, and programming of the EmbeddedICE macrocell watchpoint units. The supported scan chains are listed in Table 8-2. Table 8-2 ARM946E-S scan chain allocations...
Page 125: Table 8-3 Scan Chain 1 Bits
While debugging, the value placed in the SYSSPEED control bit determines if the ARM9E-S core executes the instruction at system speed. After the ARM946E-S has entered debug state, the first time SYSSPEED is captured and scanned out tells the debugger whether the core has entered debug state due to a breakpoint (SYSSPEED LOW) or a watchpoint (SYSSPEED HIGH).
Page 126: Table 8-4 Scan Chain 15 Addressing Mode Bit Order
Debug Support 8.4.3 Scan chain 3 This scan chain allows ARM946E-S to control an optional external boundary scan chain. You can determine the length of scan chain 3. 8.4.4 Scan chain 15 Scan chain 15 allows debug access to the CP15 register bank and allows the cache to be interrogated.
Page 127 C15.RAM Cache RAM BIST control Read/write 1101 C15.C.Ind Cache index Read/write (address/segment) 1010 C15.DC Data cache read/write (uses Read/write C15.C.Ind) 1010 C15.IC Instruction cache read/write Read/write (uses C15.C.Ind) Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 8-15...
Page 128 For a write, the register value is updated when the UPDATE-DR state is reached. For reading, return to SHIFT-DR through CAPTURE-DR to shift out the register value. Copyright © ARM Limited 2000. All rights reserved. 8-16 ARM DDI 0155A...
Page 129: Debug Access To The Caches
Writes to the DCache from the processor core by this method result in the dirty bits being set for write-back regions, and main memory is updated for write-through regions. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 8-17...
Page 130: Figure 8-6 Cache Index Register Format
Note There is no mechanism for detecting that the ICache has been updated in this way. The debugger must restore the original cache contents after executing the breakpoint. Copyright © ARM Limited 2000. All rights reserved. 8-18 ARM DDI 0155A...
Page 131: Debug Interface Signals
DBGIEBKPT, DBGDEWPT, and EDBGRQ are system requests for the ARM946E-S to enter debug state. • DBGACK is used by the ARM946E-S to flag back to the system that it is in debug state. 8.6.1 Entry into debug state on breakpoint Any instruction being fetched from memory is sampled at the end of a cycle.
Page 132 DBGDEWPT input. This signal is ORed with the internally-generated Watchpoint signal before being applied to the ARM9E-S core control logic. The timing of the input makes it unlikely that data-dependent external watchpoints are possible. Copyright © ARM Limited 2000. All rights reserved. 8-20 ARM DDI 0155A...
Page 133: Figure 8-8 Watchpoint Entry With Data Processing Instruction
In the case of a watchpoint, the PC contains a value that is five instructions on from the address of the next instruction to be executed. Therefore, if on Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 134: Figure 8-9 Watchpoint Entry With Branch
Debug Support entry to debug state, in ARM state, the instruction is scanned in and SUB PC, PC, #20 the processor restarted, execution flow returns to the next instruction in the code sequence. Fldr Dldr Eldr Mldr Wldr Ddebug Edebug1...
Page 135 Actions of the ARM9E-S in debug state When the ARM9E-S is in debug state, both memory interfaces indicate internal cycles. This ensures that the tightly-coupled SRAM within the ARM946E-S, and the AHB interface, are both quiescent, allowing the rest of the AHB system to ignore the ARM9E-S and function as normal.
Page 136: Arm9E-S Core Clock Domains
• DBGTCKEN controls debug operations. During normal operation, SYSCLKEN conditions CLK to clock the core. When the ARM946E-S is in debug state, DBGTCKEN conditions CLK to clock the core. Copyright © ARM Limited 2000. All rights reserved. 8-24 ARM DDI 0155A...
Page 137: Determining The Core And System State
Debug Support Determining the core and system state When the ARM946E-S is in debug state, you can examine the core and system state by forcing the load and store multiples into the instruction pipeline. Before you can examine the core and system state, the debugger must determine whether the processor entered debug from Thumb state or ARM state, by examining bit 4 of the EmbeddedICE-RT debug status register.
Page 138: Overview Of Embeddedice-Rt
Figure 8-10 The ARM9E-S, TAP controller, and EmbeddedICE-RT The EmbeddedICE-RT logic comprises: • two real-time watchpoint units • two independent registers: — the debug control register — the debug status register • debug comms channel. Copyright © ARM Limited 2000. All rights reserved. 8-26 ARM DDI 0155A...
Page 139 You can configure each watchpoint unit to be either a watchpoint (monitoring data accesses) or a breakpoint (monitoring instruction fetches). Watchpoints and breakpoints can be data-dependent in halt mode debug. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 8-27...
Page 140: 8.10 Disabling Embeddedice-Rt
Hard wiring the DBGEN input LOW permanently disables debug access. When DBGEN is LOW, it inhibits DBGDEWPT, DBGIEBKPT, and EDBGRQ to the core, and DBGACK from the ARM946E-S is always LOW. Copyright © ARM Limited 2000. All rights reserved. 8-28...
Page 141: 8.11 The Debug Communications Channel
Table 8-6 Coprocessor 14 register map Register name Register number Notes Comms channel status Read-only Comms channel data read For reads Comms channel data write For writes Debug status Read/write Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 8-29...
Page 142: Figure 8-11 Debug Comms Channel Status Register
From the point of view of the debugger, the registers are accessed using the scan chain in the usual way. From the point of view of the processor, these registers are accessed using coprocessor register transfer instructions. Copyright © ARM Limited 2000. All rights reserved. 8-30 ARM DDI 0155A...
Page 143: Figure 8-12 Coprocessor 14 Debug Status Register Format
DbgAbt bit to determine whether the abort has been externally or internally generated. If the DbgAbt bit is set, the abort handler initiates communication with the debugger over the comms channel. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A 8-31...
Page 144 R bit in the debug comms control register. When the debugger polls this register and sees that the R bit is clear, the data has been taken, and the process can now be repeated. Copyright © ARM Limited 2000. All rights reserved. 8-32 ARM DDI 0155A...
Page 145: 8.12 Real-Time Debug
EmbeddedICE-RT logic is configured so that a breakpoint/watchpoint causes the ARM to enter abort mode, taking the Prefetch Abort or Data Abort vectors respectively. You must be aware of a number of restrictions when the ARM is configured for real-time debugging: •...
Page 146 Further reading - debug in depth A more detailed description of the ARM9E-S debug features and JTAG interface are provided in the ARM9E-S Technical Reference Manual, Appendix D Debug in Depth. Copyright © ARM Limited 2000. All rights reserved. 8-34 ARM DDI 0155A...
Page 147: Chapter 9 Etm Interface
Chapter 9 ETM Interface This chapter describes the ARM946E-S Embedded Trace Macrocell (ETM) interface. It contains the following sections: • About the ETM interface on page 9-2 • Enabling the ETM interface on page 9-4. Copyright © ARM Limited 2000. All rights reserved.
Page 148: About The Etm Interface
The ETM interface is primarily one way. To provide code tracing, the ETM block must be able to monitor various ARM9E-S inputs and outputs. The required ARM9E-S inputs and outputs are collected and driven out from the ARM946E-S as the ETM interface.
Page 149: Figure 9-1 Arm946E-S Etm Interface
ETM Interface ETMEN ARM946E-S ETM interface registers nRESET To/from To/from ARM946E-S ARM9E-S ARM946E-S logic logic Figure 9-1 ARM946E-S ETM interface Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 150: Enabling The Etm Interface
The ETMEN input is usually driven by the ETM, and driven HIGH when you have programmed the ETM using its TAP controller. Note If you do not use an ETM in an embedded ARM946E-S design, you must tie the ETMEN input LOW to save power. Copyright © ARM Limited 2000. All rights reserved.
Page 151 Chapter 10 Test Support This chapter describes the test methodology used for the ARM946E-S synthesized logic and tightly-coupled SRAM. It contains the following sections: • About the ARM946E-S test methodology on page 10-2 • Scan insertion and ATPG on page 10-3 •...
Page 152: 10.1 About The Arm946E-S Test Methodology
To achieve a high level of fault coverage, you can use scan insertion and ATPG techniques on the ARM9E-S core and ARM946E-S control logic as part of the synthesis flow. You can use BIST to provide high fault coverage of the compiled SRAM.
Page 153: 10.2 Scan Insertion And Atpg
BIST of the SRAM. ATPG You can use the INTEST scan chain to enable an ATPG tool to access the ARM946E-S top-level inputs and outputs in an embedded design. This wrapper adds a scan source for each ARM946E-S input and a capture cell for each output. The ATPG tools use this...
Page 154 The INTEST wrapper allows the full range of BIST tests to be applied as detailed in BIST of memory arrays on page 10-5. The flow for generating the serialized patterns from ARM assembler source is supplied with the ARM946E-S implementation scripts.
Page 155: 10.3 Bist Of Memory Arrays
SRAM can be BIST tested, while code is executed over the AHB. Serial scan access to the CP15 BIST operations is also provided for production test purposes, using a special mode of operation of the INTEST wrapper. See ARM946E-S INTEST wrapper on page 10-3.
Page 156 Note ARM recommends that you do not write application code that relies on the presence of the BIST address and general registers. ARM does not guarantee to support these registers in future versions of the ARM946E-S.
Page 157: Table 10-1 Instruction Bist Address And General Registers
DBIST poke data 10.3.3 Pause modes ARM recommends that you use the following production test sequence for the SRAM: Test each SRAM using a full test. Test the BIST hardware for each SRAM. To allow testing of the BIST hardware, a pause mechanism enables you to halt the BIST test.
Page 158 • User pause on page 10-8. Note ARM recommends that you do not write application code that relies on the presence of the BIST pause mode. ARM does not guarantee to support this feature in future versions of the ARM946E-S.
Page 159: Appendix Aac Parameters
Appendix A AC Parameters This appendix lists the AC timing parameters for the ARM946E-S. It contains the following sections: • Timing diagrams on page A-2 • AC timing parameter definitions on page A-9. Copyright © ARM Limited 2000. All rights reserved.
Page 160: Figure A-1 Clock, Reset, And Ahb Enable Timing
AHB bus request and grant related timing parameters are shown in Figure A-2. HBUSREQ ovreq ohreq HLOCK ovlck ohlck HGRANT isgnt ihgnt Figure A-2 AHB bus request and grant related timing Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 161: Figure A-3 Ahb Bus Master Timing
Write data (A) HWDATA[31:0] ovwd ohwd HREADY isrdy T ihrdy HRESP OKAY OKAY isrsp T ihrsp Read data HRDATA[31:0] T ihrd isrd Figure A-3 AHB bus master timing Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 162: Figure A-4 Coprocessor Interface Timing
CHSDE WAIT/GO CHSEX LAST/ABSENT iscphs ihcphs CPLATECANCEL ovcplc ohcplc CPPASS ovcpps ohcpps LDC/MCR CPDOUT[31:0] data ovcprd ohcprd STC/MRC CPDIN[31:0] data ihcpwr iscpwr Figure A-4 Coprocessor interface timing Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 163: Figure A-5 Debug Interface Timing
DBGRNG[1:0] ovdbgrng ohdbgrng DBGRQI ovdbgrqi ohdbgrqi DBGINSTREXEC ovdbgstat ohdbgstat COMMRX COMMTX ovdbgcomm ohdbgcomm DBGEN EDBGRQ DBGEXT[1:0] isdbgin ihdbgin DBGIEBKPT isiebkpt ihiebkpt DBGDEWPT isdewpt ihdewpt Figure A-5 Debug interface timing Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 164: Figure A-6 Jtag Interface Timing
A combinatorial path timing parameter exists from the DBGSDOUT input to DBGTDO output. This is shown in Figure A-7. DBGSDOUT DBGTDO tdsd tdsh Figure A-7 DBGSDOUT to DBGTDO timing Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 165: Figure A-8 Exception And Configuration Timing
Figure A-8 Exception and configuration timing The INTEST wrapper timing parameters are shown in Figure A-9. ovso ohso issi ihsi SCANEN isscanen ihscanen TESTEN istesten ihtesten SERIALEN isserialen ihserialen Figure A-9 INTEST wrapper timing Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 166: Figure A-10 Etm Interface Timing
ETMDMORE ETMDnMREQ ETMDnRW ETMDABORT ovetmdctl ohetmdctl ETMBIGEND ETMHIVECS ovetmcfg ohetmcfg ETMCHSD[1:0] ETMCHSE[1:0] ETMPASS ETMLATECANCEL ovetmcpif ohetmcpif ETMDBGACK ETMRNGOUT[1:0] ovetmdbg ohetmdbg ETMEN isetmen ihetmen Figure A-10 ETM interface timing Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 167: Ac Timing Parameter Definitions
Rising CLK to HADDR[31:0] valid HADDR[31:0] hold time from rising CLK >0% Rising CLK to AHB control signals valid ovctl AHB control signals hold time from rising CLK >0% ohctl Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 168 Rising CLK to CPDOUT[31:0] valid ovcprd CPDOUT[31:0] hold time from rising CLK >0% ohcprd CPDIN[31:0] input setup to rising CLK iscpwr CPDIN[31:0] input hold from rising CLK ihcpwr Copyright © ARM Limited 2000. All rights reserved. A-10 ARM DDI 0155A...
Page 169 Rising CLK to DBGSDIN valid ovsdin DBGSDIN hold time from rising CLK >0% ohsdin Rising CLK to DBGTDO valid ovtdo DBGTDO hold time from rising CLK >0% ohtdo Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A A-11...
Page 170 SI input setup to rising CLK issi SI input hold from rising CLK ihsi SCANEN input setup to rising CLK isscanen SCANEN input hold from rising CLK ihscanen Copyright © ARM Limited 2000. All rights reserved. A-12 ARM DDI 0155A...
Page 171 Rising CLK to ETM debug signals valid ovetmdbg ETM debug signals hold time from rising CLK >0% ohetmdbg ETMEN input setup to rising CLK isetmen ETMEN input hold from rising CLK ihetmen Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A A-13...
Page 172 The INTEST wrapper inputs/outputs are specified as 95% of the cycle as they are production test related and expected to operate at typically 50% of the functional clock rate. Copyright © ARM Limited 2000. All rights reserved. A-14 ARM DDI 0155A...
Page 173: Appendix B Signal Descriptions
Appendix B Signal Descriptions This appendix introduces the ARM946E-S processor. It contains the following sections: • Signal properties and requirements on page B-2 • Clock interface signals on page B-3 • AHB signals on page B-4 • Coprocessor interface signals on page B-6 •...
Page 174: Signal Properties And Requirements
Signal Descriptions Signal properties and requirements In order to ensure ease of integration of the ARM946E-S into embedded applications and to simplify synthesis flow, the following design techniques have been used: • a single rising edge clock times all activity •...
Page 175: Clock Interface Signals
CLK is also a rising edge of HCLK in the AHB system that the ARM946E-S is embedded in. Must be tied HIGH in systems where CLK and HCLK are intended to be the same frequency.
Page 176: Ahb Signals
Bus grant highest priority master. Ownership of the address/control signals changes at the end of a transfer when HREADY is HIGH, so the ARM946E-S gets access to the bus when both HREADY and HGRANT are HIGH. HLOCK Output When HIGH, indicates that the ARM946E-S...
Page 177 The response can be OKAY (00), ERROR (01), RETRY (10), or SPLIT (11). HSIZE[2:0] Output Indicates the size of an ARM946E-S transfer. This Transfer size can be Byte (000), Halfword (001), or Word (010). Bit [2] is tied LOW.
Page 178: Coprocessor Interface Signals
Signal Descriptions Coprocessor interface signals Table B-3 describes the ARM946E-S coprocessor interface signals. Table B-3 Coprocessor interface signals Name Direction Description CPCLKEN Output Synchronous enable for coprocessor pipeline Coprocessor clock follower. When HIGH on the rising edge of CLK enable the pipeline follower logic can advance.
Page 179 Table B-3 Coprocessor interface signals (continued) Name Direction Description CPTBIT Output When HIGH indicates that the ARM946E-S is in Coprocessor Thumb state. When LOW indicates that the instruction Thumb ARM946E-S is in ARM state. Sampled by the coprocessor pipeline follower.
Page 180: Debug Signals
Asserted by external hardware to halt execution of Instruction the processor for debug purposes. If HIGH at the end breakpoint of an instruction fetch, it causes the ARM946E-S to enter debug state if that instruction reaches the Execute stage of the processor pipeline. DBGINSTREXEC...
Page 181 EDBGRQ and bit 1 of the debug control register. EDBGRQ Input An external debugger can force the processor into External debug debug state by asserting this signal. request Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 182: Jtag Signals
Signal Descriptions JTAG signals Table B-5 describes the ARM946E-S JTAG signals. Table B-5 JTAG signals Name Direction Description DBGIR[3:0] Output These four bits reflect the current instruction loaded TAP controller into the TAP controller instruction register. These instruction register bits change when the TAP controller is in the UPDATE-IR state.
Page 183: Miscellaneous Signals
Signal Descriptions Miscellaneous signals Table B-6 describes the ARM946E-S miscellaneous signals. Table B-6 Miscellaneous signals Name Direction Description BIGENDOUT Output When HIGH, the ARM946E-S treats bytes in memory as being in big-endian format. When LOW, memory is treated as little-endian.
Page 184: Etm Interface Signals
Signal Descriptions ETM interface signals Table B-7 describes the ARM946E-S ETM interface signals. Table B-7 ETM interface signals Name Direction Description ETMEN Input Synchronous ETM interface enable. This signal must be tied LOW if an ETM is not used. ETMBIGEND Output Big-endian configuration indication for the ETM.
Page 185 Output Coprocessor late cancel indication for the ETM. ETMPROCID[31:0] Output Process identifier for the ETM. ETMPROCIDWR Output ETMPROCID write strobe. ETMINSTRVALID Output Instruction valid indication for the ETM. Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A B-13...
Page 186: Intest Wrapper Signals
Signal Descriptions INTEST wrapper signals Table B-8 describes the ARM946E-S INTEST wrapper signals. Table B-8 INTEST wrapper signals Name Direction Description INnotEXTEST Input Selects between INTEST and EXTEST mode of the INTEST wrapper scan chain. Input Serial input data for the INTEST wrapper scan chain.
Page 187 2-25 exceptions 8-20 Auto pause 10-8 operations register 2-22 instruction boundary 8-20 size 2-8, 3-4 Automatic test pattern generator 10-3 prefetch abort 8-20 type register timing 8-19 Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A Index-i...
Page 188 Instruction RAM message transfer 8-32 enable bit 2-12 Multi-ICE load mode bit 2-12 public instructions Interlocked MCR 7-10 pullup resistors Overlapping regions Interrupts 7-13 real-time 8-33 request 8-22 Index-ii Copyright © ARM Limited 2000. All rights reserved. ARM DDI 0155A...
Page 189 2-28 write buffer control 2-15 Watchpoints 8-20 Register map, CP15 exceptions 8-22 Round robin replacement bit 2-13 timing 8-21 6-13 Write back 6-13 ARM DDI 0155A Copyright © ARM Limited 2000. All rights reserved. Index-iii...

ARM ARM946E-S Technical Reference Manual

Preface

Chapter 1 Introduction

Chapter 2 Programmer's Model

Chapter 3 Caches

Chapter 4 Protection Unit

Chapter 5 Tightly-Coupled SRAM

Chapter 6 Bus Interface Unit and Write Buffer

Chapter 7 Coprocessor Interface

Chapter 8 Debug Support

Chapter 9 ETM Interface

Chapter 10 Test Support

Appendix Aac Parameters

Appendix B Signal Descriptions

Quick Links

Related Manuals for ARM ARM946E-S

Summary of Contents for ARM ARM946E-S

Table of Contents