Figure 9-2 Read Latency With No Iem - ARM ARM1176JZF-S Technical Reference Manual

DC1
Fe1
9.2.2 Reset with no IEM
ARM DDI 0301H
ID012310
started on the AXI. In the next cycle data is returned to the AXI interface, from where it is
returned first to the level one clock domain before being forwarded to the core. Figure 9-2 shows
this.
DC2 RAW
Fe2 L2Req
The same sequence appears on the I-Side, except that there is less to do in the equivalent RAW
cycle.
The processor has the following reset inputs:
nRESETIN The nRESETIN signal is the main processor reset that initializes the
majority of the processor logic.
DBGnTRST The DBGnTRST signal is the DBGTAP reset.
nPORESETIN The nPORESETIN signal is the power-on reset that initializes the CP14
debug logic. See CP14 registers reset on page 13-25 for details.
nVFPRESETIN The nVFPRESETIN signal is the reset for the VFP block.
All of these are active LOW signals that reset logic in the processor.
The following reset signals are only used if IEM is implemented. Otherwise, these inputs are not
connected to any logic internally, and you must connect them according to your design rules:
ARESETIn
•
ARESETRWn
•
ARESETPn
•
ARESETDn.
•
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L2Req ARVALIDRW RDATARW
ARVALIDI RDATAI Data to L1

Figure 9-2 Read latency with no IEM

Clocking and Resets
Data to L1 Data to LSU
Data to PU
9-4